PEB 2466 H V2.2 Infineon Technologies, PEB 2466 H V2.2 Datasheet - Page 16

• Manufacturer Part Number: PEB 2466 H V2.2
• Description: IC SICOFI-4 SGL CHIP CMOS MQFP64
• Manufacturer: Infineon Technologies
• Series: SICOFI®r

Specifications of PEB 2466 H V2.2

• Function: CODEC Filter
• Interface: PCM, SPI
• Number Of Circuits: 4
• Voltage - Supply: 5V
• Current - Supply: 26mA
• Power (watts): 130mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-QFP
• Includes: Advanced On-Chip Functions, Digital Signal Processing (DSP) Technique, Level Metering, Tone Generators
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2466HV2.2XT; PEB2466HV22NP; PEB2466HV22XP; SP000007516; SP000007517

Hardware Reference Manual
Pin Symbol Type Function
21
22
23 RESET#
24
25
26
27
28
29
30
31
32
GNDD
MCLK
PCLK
TCA#
TCB#
V
DXA
DRA
DXB
DRB
FSC
DDD
O
O
O
O
I
I
I
I
I
I
I
I
Digital Ground
Ground reference for all digital signals.
Internally isolated from GNDA1,2,3,4.
Master Clock Input
1536, 2048, 4096 or 8192 kHz must be applied for any
operation (selected in Register XR5).
MCLK, PCLK, FSC must be synchronous.
Reset Input
Forces the device to default setting mode; active low.
Digital Supply Voltage
+5 V supply for digital circuits (use 100 nF blocking cap.).
Transmit Control Output A
PCM Interface: active if data is transmitted via DXA;
active low, open drain.
Data Transmit to PCM-Highway A
PCM Interface: PCM data for each channel is transmitted
in 8-bit bursts every 125 µs.
Data Receive from PCM-Highway A
PCM Interface: PCM data for each channel is received in
8-bit bursts every 125 µs.
Transmit Control Output B
PCM Interface: active if data is transmitted via DXB;
active low, open drain.
Data Transmit to PCM-highway B
PCM Interface: data for each channel is transmitted in
8-bit bursts every 125 µs.
Data Receive from PCM-highway B
PCM Interface: data for each channel is received in 8-bit
bursts every 125 µs.
Frame Synchronization Clock
8 kHz; reference for individual time slots, indicates start of
PCM frame; MCLK, PCLK, FSC must be synchronous.
PCM Data Clock
128 to 8192 kHz; determines the rate at which PCM data
is shifted into or out of the PCM-ports.
MCLK, PCLK, FSC must be synchronous.
7
Pin Descriptions
PEB 2466
PEF 2466
2001-02-20
Ch.
all
all
all
all
all
all
all
all
all
all
all
all