SC16C652BIB48,151 NXP Semiconductors, SC16C652BIB48,151 Datasheet - Page 10

• Manufacturer Part Number: SC16C652BIB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors
• Type: IrDAr

Specifications of SC16C652BIB48,151

• Number Of Channels: 2, DUART
• Package / Case: 48-LQFP
• Features: 2 Channels
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3276; 935274409151; SC16C652BIB48-S

Philips Semiconductors
SC16C652B_4
Product data sheet
6.6 Special feature software flow control
6.7 Hardware/software and time-out interrupts
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the SC16C652B
compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above
described flow control mechanisms, flow control characters are not placed (stacked) in the
user accessible RX data buffer or FIFO. When using a software flow control the Xon/Xoff
characters cannot be used for data transfer.
In the event that the receive buffer is overfilling and flow control needs to be executed, the
SC16C652B automatically sends an Xoff message (when enabled) via the serial TX
output to the remote modem. The SC16C652B sends the Xoff1/Xoff2 characters as soon
as received data passes the programmed trigger level. To clear this condition, the
SC16C652B will transmit the programmed Xon1/Xon2 characters as soon as receive data
drops below the programmed trigger level.
A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
character is detected, it will be placed on the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[3:0]. Note that
software flow control should be turned off when using this special mode by setting
EFR[3:0] to a logic 0.
The SC16C652B compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although
each X-Register with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register bits LCR[1:0] define the
number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[1:0] also determine the number of bits that will be used for the special
character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive
character.
The interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C652B
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR provides the current singular highest priority interrupt only.
It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition
can exist where a higher priority interrupt may mask the lower priority CTS/RTS
interrupt(s). Only after servicing the higher pending interrupt will the lower priority
CTS/RTS interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C652B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Rev. 04 — 1 September 2005
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Table 9 “SC16C652B internal registers”
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC16C652B
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