SC16C652BIB48,151 NXP Semiconductors, SC16C652BIB48,151 Datasheet - Page 21

• Manufacturer Part Number: SC16C652BIB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors
• Type: IrDAr

Specifications of SC16C652BIB48,151

• Number Of Channels: 2, DUART
• Package / Case: 48-LQFP
• Features: 2 Channels
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3276; 935274409151; SC16C652BIB48-S

Philips Semiconductors
SC16C652B_4
Product data sheet
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 16:
Table 17:
Table 18:
Table 19:
Bit
7
6
5:3
2
1:0
LCR[5]
X
X
0
0
1
LCR[2]
0
1
1
LCR[1]
0
0
1
1
Symbol
LCR[7]
LCR[6]
LCR[5:3]
LCR[2]
LCR[1:0]
LCR[4]
X
0
1
0
1
Line Control Register bits description
LCR[5:3] parity selection
LCR[2] stop bit length
LCR[1:0] word length
Word length (bits) Stop bit length (bit times)
5, 6, 7, 8
5
6, 7, 8
LCR[0]
0
1
0
1
LCR[3]
0
1
1
1
1
Description
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic 0.
Programs the parity conditions (see
Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Rev. 04 — 1 September 2005
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
Word length (bits)
5
6
7
8
1
1
2
1
2
Table
Table
19).
Table
18).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
17).
SC16C652B
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