SC16C652BIB48,151 NXP Semiconductors, SC16C652BIB48,151 Datasheet - Page 6

• Manufacturer Part Number: SC16C652BIB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors
• Type: IrDAr

Specifications of SC16C652BIB48,151

• Number Of Channels: 2, DUART
• Package / Case: 48-LQFP
• Features: 2 Channels
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3276; 935274409151; SC16C652BIB48-S

Philips Semiconductors
Table 2:
SC16C652B_4
Product data sheet
Symbol
IOW
OP2A
OP2B
RESET
RIA
RIB
RTSA
RTSB
RXA
RXB
RXRDYA 31
RXRDYB 18
TXA
TXB
TXRDYA
TXRDYB 6
15
32
9
36
41
21
33
22
5
4
7
8
43
LQFP48 HVQFN32
Pin description
Pin
12
22
7
24
-
-
23
15
4
3
-
-
5
6
-
-
…continued
Type Description
I
O
I
I
O
I
O
O
O
Write strobe (active LOW strobe). A logic 0 transition on this pin will transfer the
contents of the data bus (D0 to D7) from the external CPU to an internal register
that is defined by address bits A0 to A2.
Output 2 (user-defined). This function is associated with individual channels, A
through B. The state at these pin(s) are defined by the user and through MCR
register bit 3. INTA, INTB are set to the active mode and OP2 to logic 0 when
MCR[3] is set to a logic 1. INTA, INTB are set to the 3-state mode and OP2 to a
logic 1 when MCR[3] is set to a logic 0 (see
description”, bit 3). Since these bits control both the INTA, INTB operation and
OP2 outputs, only one function should be used at one time, INT or OP2.
Reset (active HIGH). A logic 1 on this pin will reset the internal registers and all
the outputs. The UART transmitter output and the receiver input will be disabled
during reset time. (See
initialization details.)
Ring Indicator (active LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem has received a
ringing signal from the telephone line. A logic 1 transition on this input pin will
generate an interrupt.
Request to Send (active LOW). These outputs are associated with individual
UART channels, A through B. A logic 0 on the RTS pin indicates the transmitter
has data ready and waiting to send. Writing a logic 1 in the modem control register
MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this
pin will be set to a logic 1. This pin has no effect on the UART’s transmit or receive
operation.
Receive data A, B. These inputs are associated with individual serial channel data
to the SC16C652B receive input circuits, A through B. The RX signal will be a
logic 1 during reset, idle (no data), or when the transmitter is disabled. During the
local loop-back mode, the RX input pin is disabled and TX data is connected to the
UART RX input, internally.
Receive Ready A, B (active LOW). This function provides the RX FIFO/RHR
status for individual receive channels (A to B). RXRDYn is primarily intended for
monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0 indicates
there is a receive data to read/upload, that is, receive ready status with one or
more RX characters available in the FIFO/RHR. This pin is a logic 1 when the
FIFO/RHR is empty or when the programmed trigger level has not been reached.
This signal can also be used for single mode transfers (DMA mode 0).
Transmit data A, B. These outputs are associated with individual serial transmit
channel data from the SC16C652B. The TX signal will be a logic 1 during reset,
idle (no data), or when the transmitter is disabled. During the local loop-back
mode, the TX output pin is disabled and TX data is internally connected to the
UART RX input.
Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR
status for individual transmit channels (A to B). TXRDYn is primarily intended for
monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual
channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is, at
lease one location is empty and available in the FIFO or THR. This pin goes to a
logic 1 (DMA mode 1) when there are no more empty locations in the FIFO or
THR. This signal can also be used for single mode transfers (DMA mode 0).
Rev. 04 — 1 September 2005
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Section 7.11 “SC16C652B external reset condition”
Table 20 “Modem Control Register bits
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC16C652B
for
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