SC16C652BIB48,151 NXP Semiconductors, SC16C652BIB48,151 Datasheet - Page 18

• Manufacturer Part Number: SC16C652BIB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors
• Type: IrDAr

Specifications of SC16C652BIB48,151

• Number Of Channels: 2, DUART
• Package / Case: 48-LQFP
• Features: 2 Channels
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3276; 935274409151; SC16C652BIB48-S

Philips Semiconductors
SC16C652B_4
Product data sheet
7.3.1.1 Mode 0 (FCR bit 3 = 0)
7.3.1.2 Mode 1 (FCR bit 3 = 1)
7.3.1 DMA mode
7.3.2 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR,
if FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the
Receive Holding Register (RHR) is loaded with a character.
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is below the programmed trigger level. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill
regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long
as the FIFO fill level is above the programmed trigger level.
Table 11:
Bit
7:6
5:4
3
Symbol
FCR[7:6]
FCR[5:4]
FCR[3]
FIFO Control Register bits description
Description
RCVR trigger. These bits are used to set the trigger level for the receive FIFO
interrupt.
An interrupt is generated when the number of characters in the FIFO equals
the programmed trigger level. However, the FIFO will continue to be loaded
until it is full. Refer to
Logic 0 or cleared is the default condition; TX trigger level = 16.
These bits are used to set the trigger level for the transmit FIFO interrupt.
The SC16C652B will issue a transmit empty interrupt when the number of
characters in FIFO drops below the selected trigger level. Refer to
DMA mode select.
Transmit operation in mode ‘0’: When the SC16C652B is in the 16C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY pin
will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the first
character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C652B is in 16C450 mode,
or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least
one character in the receive FIFO, the RXRDY pin will be a logic 0. Once
active, the RXRDY pin will go to a logic 1 when there are no more characters
in the receiver.
Rev. 04 — 1 September 2005
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Table
12.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC16C652B
Table
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13.