SC28L92A1B,557 NXP Semiconductors, SC28L92A1B,557 Datasheet - Page 24
![IC UART DUAL W/FIFO 44-PQFP](/photos/6/62/66269/568-44-qfp_sot307-2_sml.jpg)
SC28L92A1B,557
Manufacturer Part Number
SC28L92A1B,557
Description
IC UART DUAL W/FIFO 44-PQFP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Type
Dual UARTr
Datasheet
1.SC28L92A1B557.pdf
(73 pages)
Specifications of SC28L92A1B,557
Number Of Channels
2, DUART
Package / Case
44-MQFP, 44-PQFP
Features
False-start Bit Detection
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
0.2304 MBd
Supply Voltage (max)
3.63 V or 5.5 V
Supply Voltage (min)
2.97 V or 4.5 V
Supply Current
25 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V or 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1211
935263294557
SC28L92A1B
935263294557
SC28L92A1B
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC28L92A1B,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 7.
Table 8.
Table 9.
Table 10.
SC28L92_7
Product data sheet
RxWATCHDOG
RxRTS
control
7
7
7
7
channel mode
MR0 - Mode Register 0
MR1 - Mode Register 1
MR2 - Mode Register 2
CSR - Clock Select Register
RxINT[1]
receiver clock select code
7.2 Condensed register bit formats
RxINT[2]
6
6
6
6
Table 5.
Table 6.
Register name
Command Register
Receiver FIFO
Transmitter FIFO
Register name
Input Port Change Register
Auxiliary Control Register
Interrupt Status Register
Interrupt Mask Register
Counter/Timer Upper value
Counter/Timer Lower value
Counter/Timer Preset Upper
Counter/Timer Preset Lower
Input Port Register
Output Configuration Register
Set Output Port
Reset Output Port
Interrupt vector or GP register
ERRORMODE
Control Tx
RTSN
Registers for channels A and B
Registers supporting both channels
5
5
5
5
TxINT[1:0]
Rev. 07 — 19 December 2007
Enable Tx
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
CTSN
4
Channel A register
CRA
RxFIFOA
TxFIFOA
4
4
4
PARITYMODE
FIFOSIZE
3
3
3
3
…continued
Channel B register
CRB
RxFIFOB
TxFIFOB
Mnemonic
IPCR
ACR
ISR
IMR
CTU
CTL
CTPU
CTPL
IPR
OPCR
SOPR
ROPR
IVR/GP
EXTENDED II
transmitter clock select code
PARITYTYPE
BAUDRATE
2
2
2
2
stop bit length
TEST2
1
1
bits per character
1
1
Access
W only
R only
W only
Access
R
W
R
W
R
R
W
W
R
W
W
W
R/W
SC28L92
© NXP B.V. 2007. All rights reserved.
EXTENDED I
BAUDRATE
0
0
0
0
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