SC28L92A1B,557 NXP Semiconductors, SC28L92A1B,557 Datasheet - Page 46
![IC UART DUAL W/FIFO 44-PQFP](/photos/6/62/66269/568-44-qfp_sot307-2_sml.jpg)
SC28L92A1B,557
Manufacturer Part Number
SC28L92A1B,557
Description
IC UART DUAL W/FIFO 44-PQFP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Type
Dual UARTr
Datasheet
1.SC28L92A1B557.pdf
(73 pages)
Specifications of SC28L92A1B,557
Number Of Channels
2, DUART
Package / Case
44-MQFP, 44-PQFP
Features
False-start Bit Detection
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
0.2304 MBd
Supply Voltage (max)
3.63 V or 5.5 V
Supply Voltage (min)
2.97 V or 4.5 V
Supply Current
25 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V or 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1211
935263294557
SC28L92A1B
935263294557
SC28L92A1B
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC28L92A1B,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC28L92_7
Product data sheet
Table 58.
Bit
6
5
4
3
2
1
0
Symbol
-
RxRDYB
TxRDYB
-
-
RxRDYA
TxRDYA
ISR - Interrupt status register (address 0x5) bit description
Description
Channel B change in break.
This bit, when set, indicates that the channel B receiver has detected the
beginning or the end of a received break. It is reset when the CPU issues a
channel B reset break change interrupt command.
RxB interrupt.
This bit indicates that the channel B receiver is interrupting according to the fill
level programmed by the MR0 and MR1 registers or the watchdog timer has
timed-out. This bit has a different meaning than the receiver ready/full bit in the
status register.
TxB interrupt.
This bit indicates that the channel B transmitter is interrupting according to the
interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning
than the TxRDY bit in the status register.
Counter ready.
In the counter mode, this bit is set when the counter reaches terminal count and
is reset when the counter is stopped by a stop counter command.
In the timer mode, this bit is set once each cycle of the generated square wave
(every other time that the counter/timer reaches zero count). The bit is reset by a
stop counter command. The command, however, does not stop the
counter/timer.
Channel A change in break.
This bit, when set, indicates that the channel A receiver has detected the
beginning or the end of a received break. It is reset when the CPU issues a
channel A reset break change interrupt command.
RxA interrupt.
This bit indicates that the channel A receiver is interrupting according to the fill
level programmed by the MR0 and MR1 registers or the watchdog timer has
timed-out. This bit has a different meaning than the receiver ready/full bit in the
status register.
TxA interrupt.
This bit indicates that the channel A transmitter is interrupting according to the
interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning
than the TxRDY bit in the status register.
0 = not active
1 = active
0 = not active
1 = active
0 = not active
1 = active
0 = not active
1 = active
0 = not active
1 = active
0 = not active
1 = active
0 = not active
1 = active
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
…continued
SC28L92
© NXP B.V. 2007. All rights reserved.
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