SC28L92A1B,557 NXP Semiconductors, SC28L92A1B,557 Datasheet - Page 4
![IC UART DUAL W/FIFO 44-PQFP](/photos/6/62/66269/568-44-qfp_sot307-2_sml.jpg)
SC28L92A1B,557
Manufacturer Part Number
SC28L92A1B,557
Description
IC UART DUAL W/FIFO 44-PQFP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Type
Dual UARTr
Datasheet
1.SC28L92A1B557.pdf
(73 pages)
Specifications of SC28L92A1B,557
Number Of Channels
2, DUART
Package / Case
44-MQFP, 44-PQFP
Features
False-start Bit Detection
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
0.2304 MBd
Supply Voltage (max)
3.63 V or 5.5 V
Supply Voltage (min)
2.97 V or 4.5 V
Supply Current
25 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V or 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1211
935263294557
SC28L92A1B
935263294557
SC28L92A1B
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC28L92A1B,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
4. Block diagram
SC28L92_7
Product data sheet
Fig 1. Block diagram (80xxx mode)
The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic 0
(LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark usually
means inactive and Space means active. The voltage levels represented by the terms Mark and Space are often reversed
from those above: Mark is low voltage, and Space is high voltage.
to V
open or connect
CC
for 80xxx
D0 to D7
A0 to A3
X1/CLK
RESET
INTRN
WRN
RDN
CEN
I/M
X2
8
4
SC28L92 (80xxx mode)
R/W CONTROL
BUS BUFFER
GENERATOR
OSCILLATOR
SELECTORS
OPERATION
INTERRUPT
BAUD RATE
COUNTER/
CONTROL
ADDRESS
CONTROL
DECODE
TIMING
CLOCK
TIMER
CSRA
CSRB
XTAL
ACR
CTU
IMR
CTL
ISR
GP
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
SHIFT REGISTER
SHIFT REGISTER
TRANSMIT FIFO
DETECTORS (4)
SELECT LOGIC
OUTPUT PORT
RECEIVE FIFO
CHANGE-OF-
MRA0, 1, 2, 3
INPUT PORT
WATCHDOG
CHANNEL A
CHANNEL B
(AS ABOVE)
TRANSMIT
FUNCTION
RECEIVE
16-BYTE
16-BYTE
TIMER
STATE
OPCR
IPCR
OPR
CRA
SRA
ACR
002aad459
7
8
TxDA
RxDA
TxDB
RxDB
IP0 to IP6
OP0 to OP7
SC28L92
© NXP B.V. 2007. All rights reserved.
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