TDA8932BTW/N2,118 NXP Semiconductors, TDA8932BTW/N2,118 Datasheet - Page 13

• Manufacturer Part Number: TDA8932BTW/N2,118
• Description: IC AMP AUDIO CLASS D 32HTSSOP
• Manufacturer: NXP Semiconductors
• Type: Class Dr

Specifications of TDA8932BTW/N2,118

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Max Output Power X Channels @ Load: 55W x 1 @ 8 Ohm; 26.5W x 2 @ 4 Ohm
• Voltage - Supply: 10 V ~ 36 V, ±5 V ~ 18 V
• Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 55 W
• Available Set Gain: 36 dB
• Common Mode Rejection Ratio (min): 75 dB
• Thd Plus Noise: 0.007 %
• Operating Supply Voltage: 22 V
• Supply Current: 0.145 mA
• Maximum Power Dissipation: 5000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 8 Ohms
• Dual Supply Voltage: +/- 11 V
• Input Signal Type: Differential
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential, Single
• Supply Type: Single or Dual
• Supply Voltage (max): 36 V
• Supply Voltage (min): 10 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283479118

NXP Semiconductors
Table 5.
[1]
[2]
UJA1079_2
Product data sheet
Bit
15:13
12
11:10
9
8
7
6
5
4
3:0
Bit LHWC is set to 1 after a reset.
Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset.
Symbol
A2, A1, A0 R
RO
MC
LHWC
LHC
ENC
LSC
WBC
PDC
reserved
Mode_Control register
[2]
[1]
6.2.4 Mode_Control register
Access Power-on
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
default
001
0
00
1
0
0
0
0
0
0000
All information provided in this document is subject to legal disclaimers.
Description
register address
access status
mode control
limp home warning control
limp home control
enable control
LIN slope control
wake bias control
power distribution control
0: register set to read/write
1: register set to read only
00: Standby mode
01: Sleep mode
10: Normal mode
11: Normal mode
0: no limp home warning
1: limp home warning is set; next reset will activate LIMP output
0: LIMP pin set floating
1: LIMP pin driven LOW
0: EN pin driven LOW
1: EN pin driven HIGH in Normal mode
0: normal slope, 20 kbit/s
1: low slope, 10.4 kbit/s
0: WBIAS floating if WSEn = 0; 16 ms sampling if WSEn = 1
1: WBIAS on if WSEn = 0; 64 ms sampling if WSEn = 1
0: V1 threshold current for activating the external PNP transistor; load current
rising; I
PNP transistor; load current falling; I
1: V1 threshold current for activating the external PNP transistor; load current
rising; I
PNP transistor; load current falling; I
Rev. 02 — 27 May 2010
th(act)PNP
th(act)PNP
= 85 mA; V1 threshold current for deactivating the external
= 50 mA; V1 threshold current for deactivating the external
th(deact)PNP
th(deact)PNP
LIN core system basis chip
= 50 mA; see
= 15 mA; see
UJA1079
© NXP B.V. 2010. All rights reserved.
Figure 7
Figure 7
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