TDA8932BTW/N2,118 NXP Semiconductors, TDA8932BTW/N2,118 Datasheet - Page 14

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TDA8932BTW/N2,118

Manufacturer Part Number
TDA8932BTW/N2,118
Description
IC AMP AUDIO CLASS D 32HTSSOP
Manufacturer
NXP Semiconductors
Type
Class Dr
Datasheets

Specifications of TDA8932BTW/N2,118

Output Type
1-Channel (Mono) or 2-Channel (Stereo)
Package / Case
32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
Max Output Power X Channels @ Load
55W x 1 @ 8 Ohm; 26.5W x 2 @ 4 Ohm
Voltage - Supply
10 V ~ 36 V, ±5 V ~ 18 V
Features
Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
Mounting Type
Surface Mount
Product
Class-D
Output Power
55 W
Available Set Gain
36 dB
Common Mode Rejection Ratio (min)
75 dB
Thd Plus Noise
0.007 %
Operating Supply Voltage
22 V
Supply Current
0.145 mA
Maximum Power Dissipation
5000 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Audio Load Resistance
8 Ohms
Dual Supply Voltage
+/- 11 V
Input Signal Type
Differential
Minimum Operating Temperature
- 40 C
Output Signal Type
Differential, Single
Supply Type
Single or Dual
Supply Voltage (max)
36 V
Supply Voltage (min)
10 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935283479118
NXP Semiconductors
Table 6.
UJA1079_2
Product data sheet
Bit
15:13
12
11
10
9
8
7:6
5:4
3
2
1
Symbol
A2, A1, A0 R
RO
V1UIE
reserved
STBCL
reserved
WIC1
WIC2
reserved
RTHC
WSE1
Int_Control register
6.2.5 Int_Control register
Access Power-on
R/W
R/W
R
R/W
R
R/W
R/W
R
R/W
R/W
default
010
0
0
0
0
0
00
00
0
0
0
All information provided in this document is subject to legal disclaimers.
Description
register address
access status
V1 undervoltage interrupt enable
LIN standby control
wake-up interrupt 1 control
wake-up interrupt 2 control
reset threshold control
WAKE1 sample enable
0: register set to read/write
1: register set to read only
0: V1 undervoltage warning interrupts cannot be requested
1: V1 undervoltage warning interrupts can be requested
0: When the SBC is in Normal mode (MC = 1x):
When the SBC is in Standby/Sleep mode (MC = 0x):
1: LIN is in Lowpower mode with bus wake-up detection enabled, regardless
of the SBC mode (MC = xx). LIN wake-up interrupts can be requested.
00: wake-up interrupt 1 disabled
01: wake-up interrupt 1 on rising edge
10: wake-up interrupt 1 on falling edge
11: wake-up interrupt 1 on both edges
00: wake-up interrupt 2 disabled
01: wake-up interrupt 2 on rising edge
10: wake-up interrupt 2 on falling edge
11: wake-up interrupt 2 on both edges
0: The reset threshold is set to the 90 % V1 undervoltage detection voltage
(V
1: The reset threshold is set to the 70 % V1 undervoltage detection voltage
(V
0: sampling continuously
1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled
by WBC)
LIN is in Active mode. The wake-up flag (visible on RXDL) is cleared
regardless of the value of V
LIN is in Off mode. Bus wake-up detection is disabled. LIN wake-up
interrupts cannot be requested.
uvd
uvd
Rev. 02 — 27 May 2010
; see
; see
Table
Table
10)
10)
BAT
.
LIN core system basis chip
UJA1079
© NXP B.V. 2010. All rights reserved.
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