TDA8932BTW/N2,118 NXP Semiconductors, TDA8932BTW/N2,118 Datasheet - Page 34

• Manufacturer Part Number: TDA8932BTW/N2,118
• Description: IC AMP AUDIO CLASS D 32HTSSOP
• Manufacturer: NXP Semiconductors
• Type: Class Dr

Specifications of TDA8932BTW/N2,118

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Max Output Power X Channels @ Load: 55W x 1 @ 8 Ohm; 26.5W x 2 @ 4 Ohm
• Voltage - Supply: 10 V ~ 36 V, ±5 V ~ 18 V
• Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 55 W
• Available Set Gain: 36 dB
• Common Mode Rejection Ratio (min): 75 dB
• Thd Plus Noise: 0.007 %
• Operating Supply Voltage: 22 V
• Supply Current: 0.145 mA
• Maximum Power Dissipation: 5000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 8 Ohms
• Dual Supply Voltage: +/- 11 V
• Input Signal Type: Differential
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential, Single
• Supply Type: Single or Dual
• Supply Voltage (max): 36 V
• Supply Voltage (min): 10 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283479118

NXP Semiconductors
10. Dynamic characteristics
Table 11.
T
positive currents flow in the IC; typical values are given at V
UJA1079_2
Product data sheet
Symbol
Voltage source; pin V1
t
t
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO
t
t
t
t
t
t
t
t
t
Reset output; pin RSTN
t
t
t
Watchdog off input; pin WDOFF
t
Wake input; pin WAKE1, WAKE2
t
t
LIN transceiver; pins LIN, TXDL, RXDL
δ1
d(uvd)
det(CL)L
cy(clk)
SPILEAD
SPILAG
clk(H)
clk(L)
su(D)
h(D)
v(Q)
WH(S)
w(rst)
det(CL)L
fltr
fltr
wake
d(po)
vj
=
−
40 °C to +150
Dynamic characteristics
Parameter
undervoltage detection delay
time
LOW-level clamping detection
time
clock cycle time
SPI enable lead time
SPI enable lag time
clock HIGH time
clock LOW time
data input set-up time
data input hold time
data output valid time
chip select pulse width HIGH
reset pulse width
LOW-level clamping detection
time
filter time
filter time
wake-up time
power-on delay time
duty cycle 1
°
C; V
BAT
= 4.5 V to 28 V; V
All information provided in this document is subject to legal disclaimers.
BAT
Conditions
V
V
V
V
when SPI select falls
V
when SPI select rises
V
V
V
V
pin SDO; V
C
V
long; I
short; R
RSTN driven HIGH internally but
RSTN remains LOW
V
V
V
V
V
V
V1
V1
V1
V1
V1
V1
V1
V1
V1
V1
th(rec)RX(max)
th(dom)RX(max)
BAT
th(rec)RX(max)
th(dom)RX(max)
BAT
L
> V
Rev. 02 — 27 May 2010
= 100 pF
falling; dV
< 0.9V
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V; clock is LOW
= 2.97 V to 5.5 V; clock is LOW
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 7 V to 18 V; LSC = 0
= 5.5 V to 7 V; LSC = 0
V1
pu(RSTN)
; R
pu(RSTN)
BAT
LIN
O(V1)nom
V1
= 500
= 14 V; unless otherwise specified.
= 0.744V
= 0.76V
= 2.97 V to 5.5 V
V1
< 100 μA; no pull-up
= 0.581V
= 0.593V
= 900 Ω to 1100 Ω
/dt = 0.1 V/μs
; V1 active
Ω
; all voltages are defined with respect to ground;
BAT
BAT
BAT
BAT
; t
; t
bit
bit
= 50 μs
= 50 μs
[1]
[2]
[1]
[2]
LIN core system basis chip
7
10
113
Min
7
95
320
110
140
160
160
0
80
-
20
20
3.6
95
0.9
0.396
0.396
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UJA1079
© NXP B.V. 2010. All rights reserved.
140
-
5
140
18
40
278
Max
23
-
-
-
-
-
-
110
-
25
2.3
-
-
34 of 45
Unit
μs
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
μs
ms
μs
μs