TDA8932BTW/N2,118 NXP Semiconductors, TDA8932BTW/N2,118 Datasheet - Page 5

• Manufacturer Part Number: TDA8932BTW/N2,118
• Description: IC AMP AUDIO CLASS D 32HTSSOP
• Manufacturer: NXP Semiconductors
• Type: Class Dr

Specifications of TDA8932BTW/N2,118

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Max Output Power X Channels @ Load: 55W x 1 @ 8 Ohm; 26.5W x 2 @ 4 Ohm
• Voltage - Supply: 10 V ~ 36 V, ±5 V ~ 18 V
• Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 55 W
• Available Set Gain: 36 dB
• Common Mode Rejection Ratio (min): 75 dB
• Thd Plus Noise: 0.007 %
• Operating Supply Voltage: 22 V
• Supply Current: 0.145 mA
• Maximum Power Dissipation: 5000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 8 Ohms
• Dual Supply Voltage: +/- 11 V
• Input Signal Type: Differential
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential, Single
• Supply Type: Single or Dual
• Supply Voltage (max): 36 V
• Supply Voltage (min): 10 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283479118

NXP Semiconductors
5. Pinning information
UJA1079_2
Product data sheet
5.1 Pinning
5.2 Pin description
Table 2.
Symbol
i.c.
i.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
SCK
SCSN
i.c.
i.c.
TEST1
WDOFF
LIMP
Fig 2.
Pin configuration
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
All information provided in this document is subject to legal disclaimers.
WDOFF
Description
internally connected; should be left floating
internally connected; should be left floating
LIN transmit data input
voltage regulator output for the microcontroller (5 V or 3.3 V depending on
SBC version)
LIN receive data output
reset input/output to and from the microcontroller
interrupt output to the microcontroller
enable output
SPI data input
SPI data output
SPI clock input
SPI chip select input
internally connected; should be left floating
internally connected; should be left floating
test pin; pin should be connected to ground
WDOFF pin for deactivating the watchdog
limp home output
TEST1
SCSN
RXDL
RSTN
Rev. 02 — 27 May 2010
TXDL
INTN
SDO
SCK
SDI
EN
i.c.
i.c.
V1
i.c.
i.c.
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
UJA1079
015aaa124
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
LIN core system basis chip
BAT
VEXCTRL
TEST2
VEXCC
WBIAS
i.c.
DLIN
LIN
i.c.
GND
i.c.
i.c.
i.c.
WAKE2
WAKE1
LIMP
UJA1079
© NXP B.V. 2010. All rights reserved.
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