AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 193

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
Figure 15-16. Early Read Wait State: Write with No Hold Followed by Read with No Setup.
• if the write controlling signal has no hold time and the read controlling signal has no setup
• in NCS write controlled mode (MODE.WRITEMODE = 0), if there is no hold timing on the
• in NWE controlled mode (MODE.WRITEMODE = 1) and if there is no hold timing
time
NCS signal and the NCSRDSETUP parameter is set to zero, regardless of the read mode
(Figure 15-17 on page
an early read wait state, the write operation could not complete properly.
(NWEHOLD = 0), the feedback of the write control signal is used to control address, data,
chip select, and byte select lines. If the external write control signal is not inactivated as
expected due to load capacitances, an early read wait state is inserted and address, data
and control signals are maintained one more cycle. See
NBS0, NBS1,
A[AD_MSB:2]
(Figure 15-16 on page
A0, A1
CLK_SMC
D[15:0]
NWE
NRD
194). The write operation must end with a NCS rising edge. Without
Write cycle
193).
No hold
Early Read
Wait state
Figure 15-18 on page
No setup
Read cycle
195.
193