AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 682

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.8.2.2
Register Name:
Access Type:
Offset:
Reset Value:
• DMAnINT: DMA Channel n Interrupt
• EPnINT: Endpoint n Interrupt
• UPRSM: Upstream Resume Interrupt
• EORSM: End of Resume Interrupt
• WAKEUP: Wake-Up Interrupt
• EORST: End of Reset Interrupt
32072G–11/2011
DMA7INT
EP3INT
31
23
15
7
-
-
This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if DMAnINTE is one.
This bit is cleared when the UDDMAnSTATUS interrupt source is cleared.
This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is
one.
This bit is cleared when the interrupt source is serviced.
This bit is set when the USBB sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if UPRSME is
one.
This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be
enabled before).
This bit is set when the USBB detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if
EORSME is one.
This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt.
This bit is set when the USBB is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This
triggers an interrupt if WAKEUPE is one.
This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be
enabled before).
This bit is cleared when the Suspend (SUSP) interrupt bit is set.
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
This bit is set when a USB “End of Reset” has been detected. This triggers a USB interrupt if EORSTE is one.
This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt.
Device Global Interrupt Register
DMA6INT
UPRSM
EP2INT
30
22
14
6
-
UDINT
Read-Only
0x0004
0x00000000
DMA5INT
EORSM
EP1INT
29
21
13
5
-
DMA4INT
WAKEUP
EP0INT
28
20
12
4
-
DMA3INT
EP7INT
EORST
27
19
11
3
-
DMA2INT
EP6INT
SOF
26
18
10
2
-
DMA1INT
EP5INT
MSOF
25
17
9
1
-
EP4INT
SUSP
24
16
8
0
-
-
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