AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 321

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
Figure 19-5. Source Gather Transfer
Channel locking: Software can program a channel to keep the HSB master interface by locking
the arbitration for the master bus interface for the duration of a DMA transfer, block, or transac-
tion (single or burst).
Bus locking: Software can program a channel to maintain control of the System Bus bus by
asserting hlock for the duration of a DMA transfer, block, or transaction (single or burst). Chan-
nel locking is asserted for the duration of bus locking at a minimum.
FIFO mode: Special mode to improve bandwidth. When enabled, the channel waits until the
FIFO is less than half full to fetch the data from the source peripheral and waits until the FIFO is
greater than or equal to half full to send data to the destination peripheral. Thus, the channel can
transfer the data using System Bus bursts, eliminating the need to arbitrate for the HSB master
interface for each single System Bus transfer. When this mode is not enabled, the channel only
waits until the FIFO can transmit/accept a single System Bus transfer before requesting the
master bus interface.
Pseudo fly-by operation: Typically, it takes two System Bus cycles to complete a transfer, one
for reading the source and one for writing to the destination. However, when the source and des-
tination peripherals of a DMA transfer are on different System Bus layers, it is possible for the
DMACA to fetch data from the source and store it in the channel FIFO at the same time as the
DMACA extracts data from the channel FIFO and writes it to the destination peripheral. This
activity is known as pseudo fly-by operation. For this to occur, the master interface for both
source and destination layers must win arbitration of their HSB layer. Similarly, the source and
destination peripherals must win ownership of their respective master interfaces.
A0 + 0x034
A0 + 0x030
A0 + 0x02C
A0 + 0x028
A0 + 0x020
A0 + 0x01C
A0 + 0x018
A0 + 0x014
A0 + 0x00C
A0 + 0x008
A0 + 0x004
A0
System Memory
D10
D11
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
d7
d3
d11
d8
d4
d0
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11
CTLx.SRC_TR_WIDTH = 3'b010 (32bit/8 = 4 bytes)
SGR.SGI = 1
SGR.SGC = 4
SGR.SGI * 4 = 0x4 (Gather Increment in bytes)
Gather Boundary A0 + 0x10
Gather Increment = 4
Gather Boundary A0 + 0x38
Gather Increment = 4
Gather Boundary A0 + 0x24
Gather Increment = 4
Data Stream
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