AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 877

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AT32UC3A3128

Manufacturer Part Number
AT32UC3A3128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A3128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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31.7.5
Name :
Access Type :
Offset :
Reset Value :
32072G–11/2011
CD : Card Detection.
TOE : Time Out Error.
CRC : CRC error.
MSINT : Memory Stick interruption.
DRQ : Data request, FIFO is full (reception) or empty (transmission).
PEND : Protocol End.
0 : No card detected. This bit is cleared when the correponding bit in ISCR is set to 1.
1 : This bit is set to 1 when a Memory Stick card is inserted or removed.
0 : This bit is cleared to 0 when the corresponding bit in ISCR it set to 1.
1 : This bit is set to 1 when protol ended with time out error.
0 : No CRC error. This bit is cleared when the corresponding bit in ISCR is set to 1.
1 : This bit is set when protocol ends with CRC error.
0 : This bit is cleared to 0 when the corresponding bit in ISCR is set to 1.
1 : This bit is set to 1 when an interrupt request INT is received from Memory Stick.
0 : This bit is cleared to 0 when data access is no more required.
1 : This bit is set to 1 when data access is required (read or write).
0 : This bit is cleared to 0 when the corresponding bit in ISCR is set to 1.
1 : This bit is set to 1 when protol ended witout error.
31
23
15
7
-
-
-
-
Interrupt Status register
30
22
14
ISR
Read Only
0x10
0x00000000
6
-
-
-
-
CD
29
21
13
5
-
-
-
TOE
28
20
12
4
-
-
-
CRC
27
19
11
3
-
-
-
MSINT
26
18
10
2
-
-
-
DRQ
25
17
9
1
-
-
-
PEND
24
16
8
0
-
-
-
877

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