AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 680

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.8.2
26.8.2.1
Register Name:
Access Type:
Offset:
Reset Value:
• OPMODE2: Specific Operational mode
• TSTPCKT: Test packet mode
• TSTK: Test mode K
• TSTJ: Test mode J
• LS: Low-Speed Mode Force
32072G–11/2011
TSTPCKT
ADDEN
31
23
15
7
-
-
1: The UTMI transceiver is in the «disable bit stuffing and NRZI encoding» operational mode for test purpose.
0: The UTMI transceiver is in normal operation mode.
1: The UTMI transceiver generates test packets for test purpose.
0: The UTMI transceiver is in normal operation mode.
1: The UTMI transceiver generates high-speed K state for test purpose.
0: The UTMI transceiver is in normal operation mode.
1: The UTMI transceiver generates high-speed J state for test purpose.
0: The UTMI transceiver is in normal operation mode.
1: The low-speed mode is active.
0: The full-speed mode is active.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
USB Device Registers
Device General Control Register
TSTK
30
22
14
6
-
-
UDCON
Read/Write
0x0000
0x00000100
TSTJ
29
21
13
5
-
-
LS
28
20
12
4
-
-
UADD
27
19
11
3
-
-
SPDCONF
26
18
10
2
-
-
RMWKUP
25
17
9
1
-
-
OPMODE2
DETACH
24
16
8
0
-
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