AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 555

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
THR.TXSYNH selects the sync type to be included.
following the preamble. If MR.ONEBIT is one, a Manchester encoded zero is transmitted to indi-
cate that a new character is about to be sent. If MR.ONEBIT is zero, a synchronization pattern is
sent for the duration of three bit periods to inaugurate the new character. The sync pattern wave-
form by itself is an invalid Manchester encoding, since the transition only occurs at the middle of
the second bit period.
The Manchester Synchronization Mode bit (MR.MODSYNC) selects sync pattern, and this also
defines if the character is data (MODSYNC=0) with a zero to one transition, or a command
(MODSYNC=1) with a one to zero transition. When direct memory access is used, the sync pat-
tern can be updated on-the-fly with a modified character located in memory. To enable this
mode the Variable Synchronization of Command/Data Sync Start Frame Delimiter bit
(MR.VAR_SYNC) has to be written to one. In this case, MODSYNC is bypassed and
The Start Frame Delimiter Selector bit (MR.ONEBIT) configures the Manchester start bit pattern
Figure 25-9. Start Frame Delimiter
Manchester Drift Compensation
The Drift compensation bit (MAN.DRIFT) enables a hardware drift compensation and recovery
system that allows for sub-optimal clock drifts without further user intervention. Drift compensa-
tion is only available in 16x oversampling mode. If the RXD event is one 16
the expected edge, it is considered as normal jitter and no corrective action will be taken. If the
event is two to four 16
to three 16
th
’s after the expected edge, the current period will be prolonged by a 16
Manchester
Manchester
Manchester
encoded
encoded
encoded
th
data
data
data
’s early, the current period will be shortened by a 16
Preamble Length
Txd
Txd
Txd
is set to 0
SFD
SFD
SFD
DATA
One bit start frame delimiter
Figure 25-9
start frame delimiter
start frame delimiter
DATA
DATA
Command Sync
illustrates supported patterns.
Data Sync
th
th
. If the event is two
clock cycle from
th
.
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