SAM3N4B Atmel Corporation, SAM3N4B Datasheet - Page 108
SAM3N4B
Manufacturer Part Number
SAM3N4B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N4B
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.13.2
10.13.2.1
10.13.2.2
10.13.2.3
10.13.2.4
108
SAM3N
AND, ORR, EOR, BIC, and ORN
Syntax
Operation
Restrictions
Condition flags
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
where:
op
S
result of the operation, see
cond
Rd
Rn
Operand2
details of the options.
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations
on the values in Rn and Operand2.
The BIC instruction performs an AND operation on the bits in Rn with the complements of the
corresponding bits in the value of Operand2.
The ORN instruction performs an OR operation on the bits in Rn with the complements of the
corresponding bits in the value of Operand2.
Do not use SP and do not use PC.
If S is specified, these instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see
• do not affect the V flag.
page 80
op{S}{cond} {Rd,} Rn, Operand2
AND
ORR
EOR
BIC
ORN
is one of:
logical AND.
logical OR, or bit set.
logical Exclusive OR.
logical AND NOT, or bit clear.
logical OR NOT.
is an optional suffix. If S is specified, the condition code flags are updated on the
is an optional condition code, see
is the destination register.
is the register holding the first operand.
is a flexible second operand. See
“Conditional execution” on page
See “Conditional execution” on page
“Flexible second operand” on page 80
84.
“Flexible second operand” on
11011A–ATARM–04-Oct-10
84..
for
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