SAM3N4B Atmel Corporation, SAM3N4B Datasheet - Page 80
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SAM3N4B
Manufacturer Part Number
SAM3N4B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N4B
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.11.3
10.11.3.1
10.11.3.2
10.11.3.3
80
SAM3N
Flexible second operand
Constant
Instruction substitution
Register with optional shift
Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must be
1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3
processor only supports Thumb instructions.
Many general data processing instructions have a flexible second operand. This is shown as
Operand2 in the descriptions of the syntax of each instruction.
Operand2 can be a:
You specify an Operand2 constant in the form:
where constant can be:
In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values.
These are described in the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS,
EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is
greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect
the carry flag if Operand2 is any other constant.
Your assembler might be able to produce an equivalent instruction in cases where you specify a
constant that is not permitted. For example, an assembler might assemble the instruction CMP
Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2.
You specify an Operand2 register in the form:
where:
Rm
shift
•
•
• any constant that can be produced by shifting an 8-bit value left by any number of bits within
• any constant of the form 0x00XY00XY
• any constant of the form 0xXY00XY00
• any constant of the form 0xXYXYXYXY.
“Constant”
“Register with optional shift” on page 80
a 32-bit word
#constant
Rm {, shift}
ASR #n
LSL #n
is the register holding the data for the second operand.
is an optional shift to be applied to Rm. It can be one of:
arithmetic shift right n bits, 1 ≤ n ≤ 32.
logical shift left n bits, 1 ≤ n ≤ 31.
11011A–ATARM–04-Oct-10
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