SAM3N4B Atmel Corporation, SAM3N4B Datasheet - Page 342

• Manufacturer Part Number: SAM3N4B
• Manufacturer: Atmel Corporation

Specifications of SAM3N4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.3
Figure 24-1. General Clock Block Diagram
24.4
342
XOUT32
(Supply Controller)
Block Diagram
XIN32
XOUT
Master Clock Controller
EXTALSEL
XIN
SAM3N
RC Oscillator
Management
4/8/12 MHz
Embedded
32 kHz RC
Embedded
Resonator
Controller
3-20 MHz
Oscillator
32768 Hz
Oscillator
Status
Oscillator
Ceramic
Crystal
Crystal
Power
Fast
or
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLL.
The Master Clock Controller is made up of a clock selector and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the
selected clock between 1 and 64, and the division by 3. The PRES field in PMC_MCKR pro-
grams the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a high-speed
clock to a lower one to inform the software when the change is actually done.
Clock Generator
Control
0
1
0
1
MOSCSEL
PLL and
Divider
SLCK
Main Clock
MAINCK
PLL Clock
PLLCK
Slow Clock
SLCK
MAINCK
PLLCK
Master Clock Controller
PLLCK
MAINCK
MCK
SLCK
/1,/2,/3,/4,...,/64
Prescaler
Programmable Clock Controller
/1,/2,/4,...,/64
Prescaler
Peripherals
Clock Controller
Sleep Mode
Processor
Controller
ON/OFF
Divider
Clock
/8
ON/OFF
11011A–ATARM–04-Oct-10
Free runnning clock
Processor clock
Master clock
MCK
HCLK
int
SysTick
FCLK
periph_clk[..]
pck[..]