SAM3N4B Atmel Corporation, SAM3N4B Datasheet - Page 630

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SAM3N4B

Manufacturer Part Number
SAM3N4B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N4B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
32.5.3
32.6
32.6.1
630
Functional Description
SAM3N
Interrupt Sources
PWM Clock Generator
The PWM interrupt line is connected on one of the internal sources of the Interrupt Controller.
Using the PWM interrupt requires the Interrupt Controller to be programmed first. Note that it is
not recommended to use the PWM interrupt line in edge sensitive mode.
Table 32-3.
The PWM macrocell is primarily composed of a clock generator module and
Figure 32-2. Functional View of the Clock Generator Block Diagram
Instance
– Clocked by the system clock, MCK, the clock generator module provides 13 clocks.
– Each channel can independently choose one of the clock generator outputs.
– Each channel generates an output waveform with attributes that can be defined
PWM
independently for each channel through the user interface registers.
Peripheral IDs
31
ID
MCK
modulo n counter
PREA
PREB
PWM_MR
PWM_MR
Divider A
Divider B
DIVA
DIVB
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
clkA
clkB
11011A–ATARM–04-Oct-10
4
channels.

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