SAM3N4B Atmel Corporation, SAM3N4B Datasheet - Page 261

• Manufacturer Part Number: SAM3N4B
• Manufacturer: Atmel Corporation

Specifications of SAM3N4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16.4.5
16.4.5.1
Figure 16-3. Raising the VDDIO Power Supply
261
261
Zero-Power Power-On
Backup Power Supply
Reset Cell output
Core Power Supply
Oscillator output
Oscillator output
22 - 42 kHz RC
vddcore_nreset
periph_nreset
Fast RC
proc_nreset
bodcore_in
SAM3N
SAM3N
Power Supply Reset
Raising the Power Supply
NRST
vr_on
Note: After “proc_nreset” rising, the core starts fecthing instructions from Flash at 4 MHz.
As soon as the voltage VDDIO rises, the RC oscillator is powered up and the zero-power
power-on reset cell maintains its output low as long as VDDIO has not reached its target voltage.
During this time, the Supply Controller is entirely reset. When the VDDIO voltage becomes valid
and zero-power power-on reset signal is released, a counter is started for 5 slow clock cycles.
This is the time it takes for the 32 kHz RC oscillator to stabilize.
After this time, the voltage regulator is enabled. The core power supply rises and the brownout
detector provides the bodcore_in signal as soon as the core voltage VDDCORE is valid. This
results in releasing the vddcore_nreset signal to the Reset Controller after the bodcore_in signal
has been confirmed as being valid for at least one slow clock cycle.
Zero-Power POR
7 x Slow Clock Cycles
T
Regulator
ON
Voltage
3 x Slow Clock
Cycles
3 x Slow Clock
Cycles
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
6.5 x Slow Clock
Cycles