AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 1034

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

33.7.37
Name:
Access Type:
Offset:
Reset Value:
This register can only be written if the WPSWS2 and WPHWS2 bits are cleared in
1028.
• DTLI: Dead-Time PWMLx Output Inverted
• DTHI: Dead-Time PWMHx Output Inverted
• DTE: Dead-Time Generator Enable
• CES: Counter Event Selection
• CPOL: Channel Polarity
• CALG: Channel Alignment
9166C–AVR-08/11
CALG=0 (Left Alignment):
CALG=1 (Center Alignment):
31
23
15
7
-
-
-
-
0: The dead-time PWMLx output is not inverted.
1: The dead-time PWMLx output is inverted.
0: The dead-time PWMHx output is not inverted.
1: The dead-time PWMHx output is inverted.
0: The dead-time generator is disabled.
1: The dead-time generator is enabled.
The CES bit defines when the channel counter event occurs when the period is center aligned (CHIDx in the
Register 1” on page
0/1: The channel counter event occurs at the end of the PWM period.
0: The channel counter event occurs at the end of the PWM period.
1: The channel counter event occurs at the end of the PWM period and at half the PWM period.
0: The OCx output waveform (output from the comparator) starts at a low level.
1: The OCx output waveform (output from the comparator) starts at a high level.
0: The period is left aligned.
1: The period is center aligned.
Channel Mode Register
30
22
14
6
-
-
-
-
CMR
Read/Write
0x200 + [ch_num * 0x20]
0x00000000
1003).
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
DTLI
CES
26
18
10
2
-
”Write Protect Status Register” on page
CPRE
CPOL
DTHI
25
17
9
1
-
AT32UC3C
”Interrupt Status
CALG
DTE
24
16
8
0
-
1034