AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 904
AT32UC3C2512C Automotive
Manufacturer Part Number
AT32UC3C2512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
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• FRZCLK: Freeze USB Clock
• VBUSPO: VBUS Polarity
• OTGPADE: OTG Pad Enable
• HNPREQ: HNP Request
• SRPREQ: SRP Request
• SRPSEL: SRP Selection
• VBUSHWC: VBUS Hardware Control
• STOE: Suspend Time-Out Interrupt Enable
• HNPERRE: HNP Error Interrupt Enable
• ROLEEXE: Role Exchange Interrupt Enable
• BCERRE: B-Connection Error Interrupt Enable
• VBERRE: VBUS Error Interrupt Enable
9166C–AVR-08/11
1: The USBC is enabled.
This bit can be written to even if FRZCLK is one.
Writing a zero to this bit will enable USB clock inputs.
Writing a one to this bit will disable USB clock inputs. The resume detection will remain active. Unless explicitly stated, all
registers will become read-only.
0: The clock inputs are enabled.
1: The clock inputs are disabled.
This bit can be written to even if USBE is zero.
0: The USB_VBOF output signal is in its default mode (active high).
1: The USB_VBOF output signal is inverted (active low).
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBC (by writing a zero to the USBE bit) does not
reset this bit.
0: The OTG pad is disabled.
1: The OTG pad is enabled.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBC (by writing a zero to the USBE bit) does not
reset this bit.
When the controller is in device mode:
Writing a zero to this bit has no effect.
Writing a one to this bit will initiate a HNP (Host Negotiation Protocol).
This bit is cleared when the controller has initiated an HNP.
When the controller is in host mode:
Writing a zero to this bit will reject a HNP.
Writing a one to this bit will accept a HNP.
Writing a zero to this bit has no effect.
Writing a one to this bit will initiate an SRP when the controller is in device mode.
This bit is cleared when the controller has initiated an SRP.
0: Data line pulsing is selected as SRP method.
1: VBUS pulsing is selected as SRP method.
0: The hardware control over the USB_VBOF output pin is enabled. The USBC resets the USB_VBOF output pin when a VBUS
problem occurs.
1: The hardware control over the USB_VBOF output pin is disabled.
0: The Suspend Time-Out Interrupt (STOI) is disabled.
1: The Suspend Time-Out Interrupt (STOI) is enabled.
0: The HNP Error Interrupt (HNPERRI) is disabled.
1: The HNP Error Interrupt (HNPERRI) is enabled.
0: The Role Exchange Interrupt (ROLEEXI) is disabled.
1: The Role Exchange Interrupt (ROLEEXI) is enabled.
0: The B-Connection Error Interrupt (BCERRI) is disabled.
1: The B-Connection Error Interrupt (BCERRI) is enabled.
0: The VBUS Error Interrupt (VBERRI) is disabled.
AT32UC3C
904
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