AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 751
AT32UC3C2512C Automotive
Manufacturer Part Number
AT32UC3C2512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
- AT90CAN128_AUTOMOTIVE PDF datasheet
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #2
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #3
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28.9.7
Name:
Access Type:
Offset:
Reset Value:
• BTF: Byte Transfer Finished
• REP: Repeated Start Received
• STO: Stop Received
• SMBDAM: SMBus Default Address Match
• SMBHHM: SMBus Host Header Address Match
• SMBALERTM: SMBus Alert Response Address Match
• GCM: General Call Match
• SAM: Slave Address Match
• BUSERR: Bus Error
9166C–AVR-08/11
ORUN
BTF
31
23
15
7
-
-
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when byte transfer has completed.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a REPEATED START condition is received.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the STOP condition is received.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Default Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Host Header Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Alert Response Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the General Call Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the Slave Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a misplaced START or STOP condition has occurred.
Status Register
BUSERR
URUN
REP
30
22
14
6
-
SR
Read-only
0x18
0x000000002
SMBPECERR
STO
TRA
29
21
13
5
-
SMBTOUT
SMBDAM
28
20
12
4
-
-
SMBHHM
TCOMP
27
19
11
3
-
-
SMBALERTM
SEN
26
18
10
2
-
-
TXRDY
GCM
25
17
9
1
-
-
AT32UC3C
RXRDY
SAM
NAK
24
16
8
0
-
751
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