AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 364

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AT32UC3C2512C Automotive

Manufacturer Part Number
AT32UC3C2512C Automotive
Description
Manufacturer
Atmel Corporation
19.8.4
Register Name:
Access Type:
Offset:
Reset Value:
• DA: Decode Cycle Enable
9166C–AVR-08/11
31
23
15
7
-
-
-
-
A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus.
The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory.
1: Decode cycle is enabled.
0: Decode cycle is disabled.
High Speed Register
30
22
14
6
-
-
-
-
HSR
Read/Write
0x0C
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
-
25
17
9
1
-
-
-
-
AT32UC3C
DA
24
16
8
0
-
-
-
364

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