AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 1040

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

33.7.41
Name:
Access Type:
Offset:
Reset Value:
This register can only be written if the WPSWS3 and WPHWS3 bits are cleared in
1028.
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the
waveform period.
Only the first 20 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
9166C–AVR-08/11
– By using the PWM internal clock (CCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using the PWM internal clock (CCK) divided by one of both DIVA or DIVB divider, the formula becomes,
– By using the PWM internal clock (CCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
31
23
15
7
-
256, 512, or 1024). The resulting period formula will be:
respectively:
256, 512, or 1024). The resulting period formula will be:
(
--------------------------------------------
(
------------------------------------------------------- -
X CPRDUPD
CRPDUPD DIVA
Channel Period Update Register
×
CCK
CCK
×
30
22
14
6
-
CPRDUPD
Write-only
0x210 + [ch_num * 0x20]
-
)
)
or
(
------------------------------------------------------- -
CRPDUPD DIVB
29
21
13
5
-
CCK
×
)
28
20
12
4
-
CPRDUPD
CPRDUPD
CPRDUPD
27
19
11
3
-
26
18
10
2
-
”Write Protect Status Register” on page
25
17
9
1
-
AT32UC3C
24
16
8
0
-
1040