ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 103

• Manufacturer Part Number: ATmega325PA
• Manufacturer: Atmel Corporation

15.8
8285D–AVR–06/11
Timer/Counter Timing Diagrams
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-
TOM. There are two cases that give a transition without Compare Match.
• OCR0A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 15-8. Timer/Counter Timing Diagram, no Prescaling
Figure 15-9
Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f
Figure 15-10
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the way
up.
TCNTn
TCNTn
(clk
(clk
TOVn
TOVn
clk
clk
clk
clk
I/O
I/O
I/O
I/O
Tn
Tn
/1)
/8)
shows the same timing data, but with the prescaler enabled.
shows the setting of OCF0A in all modes except CTC mode.
Figure 15-8
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
Figure 15-7
OCn has a transition from high to low even though
MAX
MAX
Figure
15-7. When the OCR0A value is MAX the
BOTTOM
BOTTOM
clk_I/O
/8)
T0
) is therefore shown as a
BOTTOM + 1
BOTTOM + 1
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