ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 53

• Manufacturer Part Number: ATmega325PA
• Manufacturer: Atmel Corporation

11.5
11.5.1
11.5.2
8285D–AVR–06/11
Register Description
MCUSR – MCU Status Register
WDTCR – Watchdog Timer Control Register
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
Reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
• Bits 7:5 – Reserved
These bits are reserved and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
changing the prescaler bits.
Watchdog Timer” on page 51.
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
(0x60)
Read/Write
Initial Value
R
7
–
0
R
7
–
0
R
6
–
0
R
6
–
0
See ”Timed Sequences for Changing the Configuration of the
R
5
–
0
R
5
–
0
WDCE
R/W
JTRF
R/W
4
0
4
WDE
WDRF
R/W
R/W
3
0
3
See Bit Description
WDP2
R/W
BORF
R/W
2
0
2
WDP1
EXTRF
R/W
R/W
1
0
1
WDP0
R/W
PORF
0
0
R/W
0
WDTCR
MCUSR
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