ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 231

• Manufacturer Part Number: ATmega325PA
• Manufacturer: Atmel Corporation

23.9.4
23.9.5
8285D–AVR–06/11
ADCSRB – ADC Control and Status Register B
DIDR0 – Digital Input Disable Register 0
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
• Bit 7 – Reserved
This bit is reserved for future use. To ensure compatibility with future devices, this bit must be
written to zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
Table 23-6.
• Bit 7:0 – ADC7D:ADC0D: ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
Bit
(0x7B)
Read/Write
Initial Value
Bit
(0x7E)
Read/Write
Initial Value
ADTS2
0
0
0
0
1
1
1
1
ADC Auto Trigger Source Selections
ADC7D
R/W
R
7
–
0
7
0
ADC6D
ACME
ADTS1
R/W
R/W
6
0
6
0
0
0
1
1
0
0
1
1
ADC5D
R/W
R
5
0
5
–
0
ADC4D
R/W
ADTS0
R
4
0
4
–
0
0
1
0
1
0
1
0
1
ADC3D
R/W
R
3
0
3
–
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match
Timer/Counter0 Overflow
Timer/Counter Compare Match B
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
ADC2D
ADTS2
R/W
R/W
2
0
2
0
ADC1D
ADTS1
R/W
R/W
1
0
1
0
ADC0D
ADTS0
R/W
R/W
0
0
0
0
.
ADCSRB
DIDR0
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