ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 54

• Manufacturer Part Number: ATmega325PA
• Manufacturer: Atmel Corporation

8285D–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above.
Timer” on page 51.
• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in
Table 11-2.
Note:
The following code example shows one assembly and one C function for turning off the WDT.
The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that
no interrupts will occur during execution of these functions.
WDP2
to WDE even though it is set to one before the disable operation starts.
0
0
0
0
1
1
1
1
Also see
WDP1
Table
0
0
1
1
0
0
1
1
Watchdog Timer Prescale Select
Figure 29-47 on page
See ”Timed Sequences for Changing the Configuration of the Watchdog
11-2.
WDP0
0
1
0
1
0
1
0
1
Oscillator Cycles
Number of WDT
1,024K cycles
2,048K cycles
128K cycles
256K cycles
512K cycles
16K cycles
32K cycles
64K cycles
356.
Typical Time-out at
V
CC
15.4ms
30.8ms
61.6ms
0.12s
0.25s
0.49s
1.0s
2.0s
= 3.0V
Typical Time-out at
V
CC
14.7ms
29.3ms
58.7ms
0.12s
0.23s
0.47s
0.9s
1.9s
= 5.0V
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