AD9286 Analog Devices, AD9286 Datasheet - Page 17

• Manufacturer Part Number: AD9286
• Description: 8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9286

• Resolution (bits): 8bit
• # Chan: 2
• Sample Rate: 500MSPS
• Interface: Par
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

In this mode, the AD9286 can also function as a dual 8-bit,
250 MSPS converter. This may be useful in applications where
both a single 8-bit, 500 MSPS and a dual 8-bit, 250 MSPS converter
are needed. The clock management block requires that CLK±
and AUXCLK± be either 0° or 180°, relative to each other. If
this requirement is satisfied, the circuit correctly time aligns the
data coming out of each ADC core.
If the user desires to operate the AD9286 as a dual 8-bit, 250 MSPS
converter and supply only a single clock, this is achieved by
setting sample mode to simultaneous, with the AUXCLKEN
pin tied to AGND. In this mode, the two ADC cores sample
simultaneously. For a summary of all supported clocking modes,
see Table 9.
The AD9286 supports the clocking of each internal ADC with
separate clocks. By setting AUXCLKEN to DRVDD, the user
can supply a differential auxiliary clock to AUXCLK+ and
AUXCLK−. In this mode, each internal ADC core has a maximum
sample rate of 250 MSPS. This mode bypasses the internal timing
adjustment blocks.
Interleave Performance
The AD9286 achieves 500 MSPS conversion by time interleaving
two 250 MSPS ADC channels. Although this technique is sufficient
in achieving 8-bit performance, quantifiable errors are introduced.
These errors come from three sources: gain mismatch, imperfect
out-of-phase sampling, and offset mismatch between the two
channels. Distortion appears spectrally in two distinct ways: gain
and timing mismatch appear as an alias spur (see Equation 1), and
offset mismatch appears as a spur located at the Nyquist rate of the
converter (see Equation 2).
where:
f
f
where f
The magnitude of the alias spur (AS) contributed by a gain error
is shown in Equation 3.
where:
G
V
Table 9. Supported Clocking Modes
Effective Number
of Channels
One
Two
Two
One
S
IN
FSn
E
is the interleaved sample rate.
is the analog input frequency.
= Gain_Error_Ratio = 1 − V
is the full-scale voltage of Core n.
f
f
AS
ALIAS_SPUR
OFFSET_SPUR
S
GAIN
is the interleaved sample rate.
(dBc) = 20 × log(AS
= f
= f
S
/2 − f
S
/2
Maximum CLK
Frequency
500 MSPS
250 MSPS
250 MSPS
250 MSPS
IN
FS1
GAIN
/V
) = 20 × log(G
FS2
.
AUXCLK
Frequency
N/A
N/A
CLK
CLK
E
/2)
AUXCLK Phase
Relative to CLK
N/A
N/A
0°
180°
Rev. A | Page 17 of 28
(1)
(2)
(3)
AS
The magnitude of the alias spur (AS) contributed by a timing
error is shown in Equation 4.
where θ
frequency and ∆t
AS
The total magnitude of the alias spur (AS) is shown in Equation 5.
GAIN
TIMING
AUXCLKEN
Low
Low
High
High
AS
AS
, as a function of gain mismatch, is shown in Figure 30.
85
80
75
70
65
60
55
50
45
85
80
75
70
65
60
55
50
45
TIMING
TOTAL
EP
, as a function of timing error, is shown in Figure 31.
0
0
= ω
Figure 30. AS
Figure 31. AS
(dB) = 20 × log√((AS
(dBc) = 20 × log(AS
A
× ∆t
E
2
0.1
as the clock skew error.
SPI Register,
Address 0x09, Bit 3
1
0
0
0
E
(Radians), with ω
GAIN
TIMING
GAIN MISMATCH (% FS)
4
as a Function of Gain Mismatch
TIMING ERROR (ps)
0.2
as a Function of Timing Error
6
TIMING
GAIN
0.3
)
A
2
) = 20 × log(θ
as the analog input
+ (AS
8
Clock Timing Adjust
Internal
N/A
N/A
External
TIMING
0.4
10
)
2
AD9286
)
EP
/2)
0.5
12
(4)
(5)