AD9286 Analog Devices, AD9286 Datasheet - Page 19

• Manufacturer Part Number: AD9286
• Description: 8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9286

• Resolution (bits): 8bit
• # Chan: 2
• Sample Rate: 500MSPS
• Interface: Par
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9286 includes a built-in self-test feature that is designed
to enable verification of the integrity of each channel, as well as
facilitate board level debugging. A built-in self-test (BIST) feature
that verifies the integrity of the digital datapath of the AD9286
is included. Various output test options are also provided to
place predictable values on the outputs of the AD9286.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9286 signal path. Perform the BIST test after a reset to ensure
that the part is in a known state. During BIST, data from an
internal pseudorandom noise (PN) source is driven through
the digital datapath of both channels, starting at the ADC block
output. At the datapath output, CRC logic calculates a signature
from the data. The BIST sequence runs for 512 cycles and then
stops. When the test is completed, the BIST compares the signature
results with a predetermined value. If the signatures match, the
BIST sets Bit 0 of Register 0x0E, signifying that the test passed.
If the BIST test fails, Bit 0 of Register 0x0E is cleared. The outputs
are connected during this test, so the PN sequence can be observed
as it runs.
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Writing a value of 0x05 to Register 0x0E runs the BIST. This
enables the Bit 0 (BIST enable) of Register 0x0E and resets the PN
sequence generator, Bit 2 (BIST init) of Register 0x0E. At the
completion of the BIST, Bit 0 of Register 0x0E is automatically
cleared. The PN sequence can be continued from its last value
by writing a 0 to Bit 2 of Register 0x0E. However, if the PN
sequence is not reset, the signature calculation does not equal
the predetermined value at the end of the test. At that point, the
user must rely on verifying the output data.
OUTPUT TEST MODES
The output test options are described in Table 13 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back-end blocks and the
test pattern is run through the output formatting block. Some
test patterns are subject to output formatting, and some are not.
The PN generators from the PN sequence tests can be reset by
setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed
with or without an analog signal (if present, the analog signal is
ignored), but they do require an encode clock. For more
information, see the
High Speed ADCs via SPI.
AN-877
Application Note, Interfacing to
AD9286