AD9286 Analog Devices, AD9286 Datasheet - Page 23

• Manufacturer Part Number: AD9286
• Description: 8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9286

• Resolution (bits): 8bit
• # Chan: 2
• Sample Rate: 500MSPS
• Interface: Par
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Device Index and Transfer Registers
0x05
0xFF
Program Registers (May or may not be indexed by device index)
0x08
0x09
0x0D
0x0E
Register
Name
SPI port
configuration
Chip ID
(global)
Chip grade
(global)
Device
Index A
Transfer
Modes
(global)
Clock
(global)
Test mode
(local)
BIST (local)
Bit 7
(MSB)
0
Open
Open
Bit 6
LSB first
Open
100 = 500 MSPS
Bit 5
Soft reset
Speed grade ID
Reset
PN23 gen
Open
Open
Open
Bit 4
1
Reset
PN9 gen
Open
Rev. A | Page 23 of 28
8-bit chip ID
Bit 3
1
Sample
mode
0: simul-
taneous
1: inter-
leaved
Open
Bit 2
Soft reset
Open
BIST init
Internal power-down mode
Output test mode
000: off
001: midscale short
010: +FS short
011: −FS short
100: checkerboard output
101: PN23 sequence
110: PN9 sequence
111: one-/zero-word toggle
Open
00: chip run
01: full power-down
10: reserved
11: reserved
Bit 1
LSB first
ADC 2
default
Clock
boost
Open
Bit 0
(LSB)
0
ADC 1
default
Transfer
Duty cycle
stabilizer
BIST enable
Default
Value
(Hex)
0x18
0x0A
0x40
0xFF
0xFF
0x00
0x09
0x00
0x00
AD9286
Default
Notes/
Comments
Nibbles are
mirrored so
that LSB-
first or MSB-
first mode
registers
correctly,
regardless of
shift mode
Unique chip
ID used to
differentiate
devices;
read only
Unique
speed grade
ID used to
differentiate
devices;
read only
Bits are set to
determine
which on-
chip device
receives the
next write
command;
default is all
devices on
the chip
Synchronous
transfer of
data from
the master
shift register
to the slave
Determines
various
generic
modes
of chip
operation
When test
mode is set,
test data is
placed on
the output
pins in place
of normal
data
BIST mode
config