AD7949 Analog Devices, AD7949 Datasheet
AD7949
Specifications of AD7949
Available stocks
Related parts for AD7949
AD7949 Summary of contents
Page 1
... The AD7949 uses a simple SPI interface for writing to the configuration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level ...
Page 2
... Changes to Read/Write Spanning Conversion Without a Busy Indicator Section and Figure 40 ................................................... 26 Changes to Read/Write Spanning Conversion with a Busy Indicator Section and Figure 42 ................................................... 27 Changes to Evaluating AD7949 Performance Section .............. 28 Added Exposed Pad Notation to Outline Dimensions ............. 29 Changes to Ordering Guide .......................................................... 29 5/08—Rev Rev. A Changes to Ordering Guide .......................................................... 26 5/08— ...
Page 3
... AD7949 Unit Bits 0 kSPS kSPS kSPS kSPS μs μs Bits 3 LSB LSB LSB LSB LSB ppm/°C LSB LSB ppm/°C LSB 6 dB ...
Page 4
... AD7949 Parameter Conditions/Comments INTERNAL REFERENCE REF Output Voltage 2 25°C 4.096 V, @ 25°C 7 REFIN Output Voltage 2 25°C 4.096 V, @ 25°C REF Output Current Temperature Drift Line Regulation VDD = 5 V ± 5% Long-Term Drift 1000 hours Turn-On Settling Time CREF = 10 μF EXTERNAL REFERENCE ...
Page 5
... CNVH SCK DSDO t 11 SCKL t 11 SCKH t 4 HSDO t DSDO DIS t 10 CLSCK t 5 SDIN t 5 HDIN Rev Page AD7949 Typ Max Unit 2.2 μs μs μs 1.0 μ ...
Page 6
... AD7949 VDD = 2 4.5 V, VIO = 1 VDD, all specifications T Table 4. 1 Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions Data Write/Read During Conversion CNV Pulse Width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid ...
Page 7
... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev Page AD7949 ...
Page 8
... Exposed Pad NC (EPAD) (EPAD analog input, AI/O = analog input/output digital input digital output, and P = power. PIN 1 VDD 1 INDICATOR 15 VIO 14 SDO REF 2 AD7949 REFIN 3 13 SCK GND 4 12 DIN TOP VIEW GND 5 11 CNV (Not to Scale) NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY ...
Page 9
... Figure 9. Histogram Input at Code Center VDD = 2.5V REF f = 200kSPS 19.9kHz IN SNR = 84.2dB SINAD = 82.4dB THD = –84dB SFDR = 85dB SECOND HARMONIC = –100dB THIRD HARMONIC = –85dB FREQUENCY (kHz) Figure 10. 20 kHz FFT VDD = 2.5 V REF AD7949 16,384 = VDD = VDD = 2. 2003 2004 100 ...
Page 10
... AD7949 VDD = V = 5V, –0.5dB REF VDD = V = 5V, –10dB REF VDD = V = 2.5V, –0.5dB 65 REF VDD = V = 2.5V, –10dB REF 100 FREQUENCY (kHz) Figure 11. SNR vs. Frequency 88 SNR SINAD ENOB 1.0 1.5 2.0 2.5 3.0 3.5 4.0 REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage 20kHz ...
Page 11
... VDD = 2.5V, 85° VDD = 2.5V, 25°C 10 VDD = 5V, 85°C VDD = 5V, 25°C 5 VDD = 3.3V, 85°C VDD = 3.3V, 25° SDO CAPACITIVE LOAD (pF) Figure 22. t Delay vs. SDO Capacitance Load and Supply DSDO AD7949 100 5.0 5.5 180 160 140 120 100 ...
Page 12
... AD7949 TERMINOLOGY Least Significant Bit (LSB) The LSB is the smallest increment that can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is V (V) = REF LSB N 2 Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ ...
Page 13
... The AD7949 provides the user with an on-chip track-and-hold and does not exhibit pipeline delay or latency. The AD7949 is specified from 2 5.5 V and can be interfaced to any 1 digital logic family. The part is housed in a 20-lead × LFCSP that combines space savings and allows flexible configurations ...
Page 14
... INx− /2), the data outputs are REF twos complement. The ideal transfer characteristic for the AD7949 is shown in Figure 24 and for both unipolar and bipolar ranges with the internal 4.096 V reference. Table 7. Output Codes and Ideal Input Voltages ...
Page 15
... ADA4841-x V– IN0 IN[7:1] V+ AD7949 3 ADA4841-x V– COM GND Figure 26. Typical Application Diagram Using Bipolar Input Rev Page 1.8V TO VDD 100nF VIO DIN MOSI SCK SCK MISO SDO SS CNV 1.8V TO VDD 100nF 100nF VIO DIN MOSI SCK SCK SDO MISO CNV SS AD7949 ...
Page 16
... ANALOG INPUTS Input Structure Figure 27 shows an equivalent circuit of the input structure of the AD7949. The two diodes, D1 and D2, provide ESD protec- tion for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this causes the diodes to become forward biased and to start conducting current ...
Page 17
... CH3+ (–) CH3– (+) Sequencer The AD7949 includes a channel sequencer useful for scanning channels in a repeated fashion. Refer to the Channel Sequencer section for further details of the sequencer operation. Source Resistance When the source impedance of the driving circuit is low, the AD7949 can be driven directly. Large source impedances significantly affect the ac performance, especially THD ...
Page 18
... AD7949 GND pin. The internal reference is temperature-compensated to within 10 mV. The reference is trimmed to provide a typical drift of ±10 ppm/°C. Connect the AD7949 as shown in Figure 30 for either a 2 4.096 V internal reference. Rev Page Data Sheet 10µF ...
Page 19
... AD8605. The placement of the reference decoupling capacitor is also impor- tant to the performance of the AD7949, as explained in the Layout section. Mount the decoupling capacitor on the same side as the ADC at the REF pin with a thick PCB trace. The GND ...
Page 20
... AD7949 POWER SUPPLY The AD7949 uses two power supply pins: an analog and digital core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7949 is independent of power supply sequencing between VIO and VDD ...
Page 21
... Data Sheet DIGITAL INTERFACE The AD7949 uses a simple 4-wire interface and is compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x, SHARC®, ADSP-219x, and ADSP-218x. The interface uses the CNV, DIN, SCK, and SDO signals and allows CNV, which initiates the conversion independent of the readback timing ...
Page 22
... CFG register. Note that, at power-up, the CFG register is undefined and two dummy conversions are required to update the register. To preload the CFG register with a factory setting, hold DIN high for two conversions. Thus CFG[13:0] = 0x3FFF. This sets the AD7949 for the following ...
Page 23
... REQUIRED TO RETURN SDO TO HIGH-Z. 3. WITH THE SEQUENCER ENABLED, THE NEXT ACQUISITION PHASE WILL BE FOR IN0 AFTER THE LAST CHANNEL SET IN CFG[9:7] IS CONVERTED. Figure 36. General Interface Timing for the AD7949 Without a Busy Indicator When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − ...
Page 24
... A TOTAL OF 15 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 29 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 37. General Interface Timing for the AD7949 With a Busy Indicator generation requires either a high impedance or a remaining bit high-to-low transition ...
Page 25
... Data Sheet CHANNEL SEQUENCER The AD7949 includes a channel sequencer useful for scanning channels in a repeated fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced. The sequencer starts with IN0 and finishes with IN[7:0] set in CFG[9:7]. For paired channels, the channels are paired depend- ing on the last channel set in CFG[9:7] ...
Page 26
... SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 27 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 14TH OR 28TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPEDANCE. Figure 40. Serial Interface Timing for the AD7949 Without a Busy Indicator low after t host also must enable the MSB of the CFG register at this time (if necessary) to begin the CFG update ...
Page 27
... BEIGN CFG ( HSDO DIS t DSDO MSB MSB – 1 BEGIN DATA (n – Figure 42. Serial Interface Timing for the AD7949 with a Busy Indicator Rev Page time elapses for the next conversion. All 14 bits of DATA elapses lost. DATA th ( CONV t ...
Page 28
... The pinout of the AD7949, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7949 is used as a shield ...
Page 29
... LFCSP_VQ 20-Lead LFCSP_VQ Evaluation Board Controller Board Rev Page 2.65 EXPOSED PAD 2. 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option Ordering Quantity CP-20-4 Tray, 490 CP-20-4 Reel, 1,500 AD7949 ...
Page 30
... AD7949 NOTES Rev Page Data Sheet ...
Page 31
... Data Sheet NOTES Rev Page AD7949 ...
Page 32
... AD7949 NOTES ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07351-0-8/11(C) Rev Page Data Sheet ...