AD7949 Analog Devices, AD7949 Datasheet - Page 8

• Manufacturer Part Number: AD7949
• Description: 14-Bit, 8-Channel, 250 kSPS PulSAR ADC
• Manufacturer: Analog Devices

Specifications of AD7949

• Resolution (bits): 14bit
• # Chan: 8
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: SAR
• Pkg Type: CSP

AD7949
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1, 20
2
3
4, 5
6 to 9
10
11
12
13
14
15
16 to 19
21
(EPAD)
1
AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
Mnemonic
VDD
REF
REFIN
GND
IN4 to IN7
COM
CNV
DIN
SCK
SDO
VIO
IN0 to IN3
Exposed Pad
(EPAD)
Type
P
AI/O
AI/O
P
AI
AI
DI
DI
DI
DO
P
AI
NC
1
Description
Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with
10 μF and 100 nF capacitors.
When using the internal reference for 2.5 V output, the minimum should be 3.0 V.
When using the internal reference for 4.096 V output, the minimum should be 4.5 V.
Reference Input/Output. See the Voltage Reference Output/Input section.
When the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or
4.096 V.
When the internal reference is disabled and the buffer is enabled, REF produces a buffered
version of the voltage present on the REFIN pin (4.096 V maximum), useful when using low cost,
low power references.
For improved drift performance, connect a precision reference to REF (0.5 V to VDD).
For any reference method, this pin needs decoupling with an external 10 μF capacitor
connected as close to REF as possible. See the Reference Decoupling section.
Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input
section.
When using the internal reference, the internal unbuffered reference voltage is present and
needs decoupling with a 0.1 μF capacitor.
When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is
buffered to the REF pin as described above.
Power Supply Ground.
Channel 4 through Channel 7 Analog Inputs.
Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode
point of 0 V or V
Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is
held high, the busy indictor is enabled.
Data Input. This input is used for writing to the 14-bit configuration register. The configuration
register can be written to during and after conversion.
Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN
in an MSB first fashion.
Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar
modes, conversion results are straight binary; in bipolar modes, conversion results are twos
complement.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
Channel 0 through Channel 3 Analog Inputs.
The exposed pad is not connected internally. For increased reliability of the solder joints, it is
recommended that the pad be soldered to the system ground plane.
REFIN
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
GND
GND
VDD
REF
INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS, IT
IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SYSTEM
GROUND PLANE.
1
2
3
4
5
Figure 4. Pin Configuration
REF
Rev. C | Page 8 of 32
(Not to Scale)
/2 V.
AD7949
TOP VIEW
PIN 1
INDICATOR
15 VIO
14 SDO
13 SCK
12 DIN
11 CNV
Data Sheet