AD7949 Analog Devices, AD7949 Datasheet - Page 24

• Manufacturer Part Number: AD7949
• Description: 14-Bit, 8-Channel, 250 kSPS PulSAR ADC
• Manufacturer: Analog Devices

Specifications of AD7949

• Resolution (bits): 14bit
• # Chan: 8
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: SAR
• Pkg Type: CSP

AD7949
GENERAL TIMING WITH A BUSY INDICATOR
Figure 37 details the timing for all three modes: read/write
during conversion (RDC), read/write after conversion (RAC),
and read/write spanning conversion (RSC). Note that the gating
item for both CFG and data readback is at the end of conversion
(EOC). As detailed previously, the data access should occur up
to safe data reading/writing time, t
not written to prior to EOC, it is discarded and the current
configuration remains.
At the EOC, if CNV is low, the busy indicator is enabled. In
addition, to generate the busy indicator properly, the host must
assert a minimum of 15 SCK falling edges to return SDO to
high impedance because the last bit on SDO remains active.
Unlike the case detailed in the General Timing Without a Busy
Indicator section, if the conversion result is not read out fully
prior to EOC, the last bit clocked out remains. If this bit is low,
the busy signal indicator cannot be generated because the busy
RDC
RAC
RSC
NOTES
1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR.
2. A TOTAL OF 15 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,
A TOTAL OF 29 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
PHASE
SDO
SDO
SCK
SDO
SCK
CNV
SCK
CNV
CNV
DIN
DIN
DIN
POWER
UP
(n – 2) UNDEFINED
1
CONVERSION
DATA (n – 3)
t
CONV
XXX
XXX
15
t
CYC
EOC
DATA
NOTE 1
NOTE 1
NOTE 1
(n – 1) UNDEFINED
ACQUISITION
1
1
START OF CONVERSION
CFG (n)
. If the full CFG word is
DATA (n – 2)
Figure 37. General Interface Timing for the AD7949 With a Busy Indicator
DATA (n – 2)
NOTE 2
XXX
XXX
15
CFG (n)
n
(SOC)
NOTE 2
n + 1
(n – 1) UNDEFINED
1
DATA (n – 2)
CONVERSION
t
DATA
CFG (n)
XXX
DATA (n – 2)
NOTE 2
15
XXX
15
Rev. C | Page 24 of 32
EOC
ACQUISITION
1
1
CFG (n + 1)
DATA (n – 1)
DATA (n – 1)
(n)
XXX
XXX
15
n
CFG (n + 1)
generation requires either a high impedance or a remaining bit
high-to-low transition. Because most SPI hosts are usually
limited to 8-bit or 16-bit bursts, this should not be an issue.
Additional clocks are not a concern because SDO remains high
impedance after the 15
The SCK can idle high or low depending on the CPOL and
CPHA settings if SPI is used. A simple solution is to use CPOL
= CPHA = 1 (not shown) with SCK idling high.
From power-up, in any read/write mode, the first three conver-
sion results are undefined because a valid CFG does not take
place until the 2
required. Also, if the state machine writes the CFG during the
power-up state (RDC shown), the CFG register needs to be
rewritten again at the next phase. Note that the first valid data
occurs in Phase (n + 1) when the CFG register is written during
Phase (n − 1).
n + 1
CONVERSION
1
DATA (n – 1)
CFG (n + 1)
XXX
DATA (n – 1)
(n)
15
XXX
15
nd
EOC
EOC; thus, two dummy conversions are
ACQUISITION
1
CFG (n + 2)
1
(n + 1)
DATA (n)
th
DATA (n)
falling edge.
15
CFG (n + 2)
n
n + 1
CONVERSION
1
CFG (n + 2)
DATA (n)
(n + 1)
DATA (n)
15
15
EOC
Data Sheet
ACQUISITION
1
1
CFG (n + 3)
DATA (n + 1)
DATA (n + 1)
(n + 2)
CFG (n + 3)