AD7949 Analog Devices, AD7949 Datasheet - Page 23

• Manufacturer Part Number: AD7949
• Description: 14-Bit, 8-Channel, 250 kSPS PulSAR ADC
• Manufacturer: Analog Devices

Specifications of AD7949

• Resolution (bits): 14bit
• # Chan: 8
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
GENERAL TIMING WITHOUT A BUSY INDICATOR
Figure 36 details the timing for all three modes: read/write
during conversion (RDC), read/write after conversion (RAC),
and read/write spanning conversion (RSC). Note that the gating
item for both CFG and data readback is at the end of conversion
(EOC). At EOC, if CNV is high, the busy indicator is disabled.
As detailed previously in the Digital Interface section, the data
access should occur up to safe data reading/writing time, t
If the full CFG word was not written to prior to EOC, it is dis-
carded and the current configuration remains. If the conversion
result is not read out fully prior to EOC, it is lost as the ADC
updates SDO with the MSB of the current conversion. For
detailed timing, refer to Figure 39 and Figure 40, which depict
reading/writing spanning conversion with all timing details,
including setup, hold, and SCK.
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
2. A TOTAL OF 14 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 28 SCK FALLING EDGES IS
3. WITH THE SEQUENCER ENABLED, THE NEXT ACQUISITION PHASE WILL BE FOR IN0 AFTER THE LAST CHANNEL SET IN CFG[9:7] IS CONVERTED.
RDC
RAC
RSC
REQUIRED TO RETURN SDO TO HIGH-Z.
PHASE
SDO
SDO
SCK
SDO
SCK
CNV
SCK
CNV
CNV
DIN
DIN
DIN
POWER
UP
MSB
XXX
(n – 2) UNDEFINED
1
CONVERSION
DATA (n – 3)
XXX
t
XXX
CONV
14
t
CYC
EOC
NOTE 1
NOTE 1
NOTE 1
(n – 1) UNDEFINED
ACQUISITION
1
1
Figure 36. General Interface Timing for the AD7949 Without a Busy Indicator
DATA (n – 2)
DATA (n – 2)
CFG (n)
NOTE 2
CFG (n)
XXX
XXX
14
n
SOC
n + 1
(n – 1) UNDEFINED
DATA (n – 2)
1
CONVERSION
CFG (n)
t
DATA (n – 2)
DATA
CFG (n)
XXX
NOTE 2
NOTE 2
14
XXX
14
DATA
Rev. C | Page 23 of 32
EOC
.
ACQUISITION
1
1
CFG (n + 1)
DATA (n – 1)
DATA (n – 1)
CFG (n + 1)
(n)
XXX
XXX
MSB
14
XXX
n
When CNV is brought low after EOC, SDO is driven from high
impedance to the MSB. Falling SCK edges clock out bits starting
with MSB − 1.
The SCK can idle high or low depending on the clock polarity
(CPOL) and clock phase (CPHA) settings if SPI is used. A simple
solution is to use CPOL = CPHA = 0 as shown in Figure 36 with
SCK idling low.
From power-up, in any read/write mode, the first three conver-
sion results are undefined because a valid CFG does not take
place until the 2
required. Also, if the state machine writes the CFG during the
power-up state (RDC shown), the CFG register needs to be
rewritten again at the next phase. Note that the first valid data
occurs in Phase (n + 1) when the CFG register is written during
Phase (n − 1).
n + 1
CFG (n + 1)
DATA (n – 1)
CFG (n + 1)
1
CONVERSION
DATA (n – 1)
XXX
XXX
(n)
14
14
nd
EOC
EOC; thus two dummy conversions are
ACQUISITION
1
1
CFG (n + 2)
DATA (n)
CFG (n + 2)
(n + 1)
DATA (n)
14
MSB
n
(n)
n + 1
CFG (n + 2)
CONVERSION
1
CFG (n + 2)
DATA (n)
(n + 1)
DATA (n)
14
14
EOC
ACQUISITION
1
1
CFG (n + 3)
DATA (n + 1)
DATA (n + 1)
CFG (n + 3)
(n + 2)
AD7949
n