AD7762 Analog Devices, AD7762 Datasheet
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AD7762
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AD7762 Summary of contents
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... V differential biased around a common mode This common-mode biasing can be achieved using the on-chip differential amplifier, further reducing the external signal conditioning requirements. The AD7762 is available in an exposed paddle, 64-lead TQFP and is specified over the industrial temperature range from −40°C to +85°C. Table 1. Related Devices Part No ...
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... Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 9 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 13 AD7762 Interface............................................................................ 14 Reading Data............................................................................... 14 Sharing the Parallel Bus ............................................................. 14 Writing to the AD7762 .............................................................. 14 Reading Status and Other Registers......................................... 14 Clocking the AD7762 ................................................................ 15 Example 1 .................................................................................... 15 Example 2 .................................................................................... 15 Driving the AD7762....................................................................... 16 Using the AD7762 ...................................................................... 17 REVISION HISTORY 8/05— ...
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... Bits 0.00076 % typ 0.014 % typ 0.02 % max 0.015 % typ 0.019 %/°C typ 0.0002 %/°C typ 47 μs typ 91.5 μs typ 358 μs typ ±2 V p-p ±3. typ 55 pF typ AD7762 ...
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... SNR specifications in dBs are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 3 While the AD7762 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated. 4 Tested with a 400 μA load current. ...
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... CS high period between address and data ns min Data setup time ns min Data hold time DATA MSW Figure 2. Parallel Interface Timing Diagram REGISTER ADDRESS Figure 3. AD7762 Register Write Rev Page AD7762 LSW + STATUS REGISTER DATA ...
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... AD7762 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameters AV to GND DD1 AV –AV to GND DD2 DD4 DV to GND GND DRIVE GND IN+ IN– 1 Digital input voltage to GND MCLK to MCLKGND GND REF AGND to DGND Input Current to Any Pin ...
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... AV 12 DD4 DD2 AV 15 DD2 Figure 4. 64-Lead TQFP Pin Configuration ). See the Reference Voltage Filtering section for more details. Rev Page AD7762 48 DB12 47 DB13 46 DB14 DB15 DRIVE DGND 43 42 DGND ...
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... Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and from the AD7762. If this pin is low when CS is low, a read takes place. If this pin is high and CS is low, a write occurs. See the AD7762 Interface section for more details. ...
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... SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For the AD7762 defined ...
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... AD7762 TYPICAL PERFORMANCE CHARACTERISTICS 2 DD1 DD DRIVE DD2 are generated from 65536 samples using a 7-term Blackman-Harris window. 0 –25 –50 –75 –100 –125 –150 –175 –200 0 4000 8000 12000 FREQUENCY (Hz) Figure 5. Normal Mode FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation 0 – ...
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... Figure 16. Low Power SNR vs. Decimation Rate, 1 kHz Input Tone Rev Page 60000 120000 180000 240000 FREQUENCY (Hz) 0 60000 120000 180000 240000 FREQUENCY (Hz) –60dB –6dB –0.5dB 0 64 128 192 DECIMATION RATE (x) AD7762 300000 300000 256 ...
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... AD7762 4500 4000 3500 3000 2500 2000 1500 1000 500 0 8385222 8385238 8385254 24-BIT CODE Figure 17. Normal Mode, 24-Bit Histogram, 256× Decimation 0.0010 +85°C 0.0005 +25°C 0 –40°C –0.0005 –0.0010 0 4194304 8388608 24-BIT CODE Figure 18. 24-Bit INL, Normal Mode ...
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... The AD7762 employs three FIR filters in series. By using different combinations of decimation ratios and filter selection and bypassing, data can be obtained from the AD7762 at a large range of data rates. The first filter receives data from the modulator at ICLK MHz where it is decimated by four to output data at ICLK/4 MHz ...
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... Downloading a User-Defined Filter section. The AD7762 Registers section contains the register addresses and more details. Figure 3 shows a write operation to the AD7762. The RD /WR line is held high while the CS line is brought low for a minimum of 4 ICLK periods. The register address is latched during this period ...
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... CLOCKING THE AD7762 The AD7762 requires an external low jitter clock source. This signal is applied to the MCLK pin, and the MCLKGND pin is used to sense the ground from the clock source. An internal clock signal (ICLK) is derived from the MCLK input signal. The ICLK controls the internal operations of the AD7762. The maximum ICLK frequency is 20 MHz, but due to an internal clock divider, a range of MCLK frequencies can be used ...
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... To obtain maximum performance from the AD7762 advisable to drive the ADC with differential signals. shows how a bipolar, single-ended signal biased around ground can drive the AD7762 with the use of an external op amp, such as the AD8021. With a 4.096 V reference supply must be provided to the reference buffer (AV ) ...
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... The user can then download a different filter, if required (see Downloading a User-Defined Filter). Values for gain, offset, and overrange threshold registers can be written or read at this stage. BIAS RESISTOR SELECTION The AD7762 requires a resistor to be connected between the R pin and AGND1. The value for this resistor is dependant BIAS CPA CPB1/2 on the reference voltage being applied to the device ...
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... AD7762 DECOUPLING AND LAYOUT RECOMMENDATIONS Due to the high performance nature of the AD7762, correct decoupling and layout techniques are required to obtain the performance as stated within this datasheet. Figure 29 shows a simplified connection diagram for the AD7762. INA+ INA– OUTA– OUTA+ VIN+ ...
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... Pin 30 requires capacitor. REFERENCE VOLTAGE FILTERING A low noise reference source, such as the ADR431 (2 ADR434 (4.096 V), is suitable for use with the AD7762. The reference voltage supplied to the AD7762 should be decoupled and filtered, as shown in Figure 30. ...
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... AD7762 PROGRAMMABLE FIR FILTER As previously mentioned, the third FIR filter on the AD7762 is user programmable. The default coefficients that are loaded on reset are given in Table 10 and the frequency responses are shown in Figure 31. The frequencies quoted in Figure 31 scale directly with the output data rate. ...
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... DOWNLOADING A USER-DEFINED FILTER As previously mentioned, the filter coefficients are 27 bits in length; 1 sign and 26 magnitude bits. Because the AD7762 has a 16-bit parallel bus, the coefficients are padded with 5 MSB 0s to generate a 32-bit word and split into two 16-bit words for downloading. The first 16-bit word for each coefficient becomes (00000, Sign bit, Magnitude [25:16]), while the second word becomes (Magnitude [15:0]) ...
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... Table 14 lists the 16-bit words the user would write to the AD7762 to set up the ADC and download this filter, assuming an output data rate of 625 kHz has already been selected. Table 14. Word 0x0001 Word 2 0x8079 Byte 3 Byte 4 0x032B 96 ...
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... PD Power Down. Setting this bit powers down the AD7762, reducing the power consumption to 6.35 mW. 2 LPWR Low Power. If this bit is set, the AD7762 is operating in a low power mode. The power consumption is reduced for reduction in noise performance Write 1 to this bit. ...
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... OVR If the current analog input exceeds the current overrange threshold, this bit is set When downloading a user filter to the AD7762, a checksum is generated. This checksum is compared to the one downloaded following the coefficients. If these checksums agree, this bit is set. 6 Filter OK When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This generated checksum is compared to the one downloaded ...
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... Dimensions shown in millimeters Package Description 64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) 64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) Evaluation Board Rev Page 10.20 10.00 SQ EXPOSED 9.80 BSC SQ PAD BOTTOM VIEW (PINS UP 0.50 0.38 BSC 0.32 LEAD PITCH 0.22 Package Option SV-64-4 SV-64-4 AD7762 7.50 ...
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... AD7762 NOTES Rev Page ...
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... Rev Page AD7762 ...
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... AD7762 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05477–0–8/05(0) Rev Page ...