AD7762 Analog Devices, AD7762 Datasheet - Page 15

• Manufacturer Part Number: AD7762
• Description: Parallel Interface, 625 kSPS, 24-Bit Sigma-Delta A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7762

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (1.6Vref) p-p,4 V p-p,6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

CLOCKING THE AD7762
The AD7762 requires an external low jitter clock source. This
signal is applied to the MCLK pin, and the MCLKGND pin is
used to sense the ground from the clock source. An internal
clock signal (ICLK) is derived from the MCLK input signal.
The ICLK controls the internal operations of the AD7762. The
maximum ICLK frequency is 20 MHz, but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are two ways to generate the ICLK:
These options are selected from the control register (see the
AD7762 Registers section for more details). On power-up, the
default is ICLK = MCLK/2 to ensure that the part can handle
the maximum MCLK frequency of 40 MHz. For output data
rates equal to those used in audio systems, a 12.288 MHz ICLK
frequency can be used. As shown in
of 192 kHz, 96 kHz, and 48 kHz are achievable with this ICLK
frequency. As mentioned previously, this ICLK frequency can
be derived from different MCLK frequencies.
The MCLK jitter requirements depend on a number of factors
and are given by
where:
OSR = Over-sampling ratio =
f
SNR (dB) = Target SNR
EXAMPLE 1
This example can be taken from Table 6, where:
ODR = 625 kHz
f
f
SNR = 108 dB
This is the maximum allowable clock jitter for a full-scale,
250 kHz input tone with the given ICLK and output data rate.
IN
ICLK
IN
= Maximum input frequency
(max) = 250 kHz
= 20 MHz
ICLK = MCLK ( CDIV = 1)
ICLK = MCLK /2 ( CDIV = 0)
t
t
j
j
(
(
rms
rms
)
)
=
=
2
2
×
×
π
π
×
×
250
f
IN
OSR
32
×
×
10
10
SNR
3
×
20
ODR
(
f
10
dB
ICLK
)
6
=
Table 6, output data rates
3
6 .
ps
Rev. 0 | Page 15 of 28
EXAMPLE 2
Take a second example from Table 6, where:
ODR = 48 kHz
f
f
SNR = 120 dB
The input amplitude also has an effect on these jitter figures.
If, for example, the input level was 3 dB below full scale, the
allowable jitter would be increased by a factor of √2, increasing
the first example to 2.53 ps rms. This happens when the
maximum slew rate is decreased by a reduction in amplitude.
Figure 23 and Figure 24 illustrate this point, showing the
maximum slew rate of a sine wave of the same frequency but
with different amplitudes.
ICLK
IN
(max) = 19.2 kHz
Figure 23. Maximum Slew Rate of Sine Wave with Amplitude of 2 V p-p
= 12.288 MHz
Figure 24. Maximum Slew Rate of Same Frequency Sine Wave with
–0.5
–1.0
–0.5
–1.0
t
0.5
0.5
j
(
1
0
1
0
rms
)
=
2
×
π
×
19
2 .
Amplitude of 1 V p-p
256
×
10
3
×
10
6
=
133
ps
AD7762