AD7762 Analog Devices, AD7762 Datasheet - Page 5

• Manufacturer Part Number: AD7762
• Description: Parallel Interface, 625 kSPS, 24-Bit Sigma-Delta A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7762

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (1.6Vref) p-p,4 V p-p,6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

TIMING SPECIFICATIONS
AV
Table 3.
Parameter
f
f
t
t
t
t
t
t
t
t
t
t
t
t
1
2
TIMING DIAGRAMS
MCLK
ICLK
1
2
3
4
5
6
7
8
9
10
11
12
t
When ICLK = MCLK, DRDY pulse width depends on the mark/space ratio of applied MCLK.
1, 2
ICLK
DD1
= 1/f
= DV
ICLK
.
DD
= V
Limit at T
1
40
500
20
0.5 × t
10
3
(0.5 × t
t
t
3
11
4 × t
4 × t
5
0
DRIVE
ICLK
ICLK
RD/WR
D[0:15]
DRDY
ICLK
ICLK
= 2.5 V, AV
RD/WR
D[0:15]
CS
ICLK
ICLK
CS
) + 16 ns
MIN
, T
MAX
DD2
t
11
= AV
t
1
DD3
t
2
REGISTER ADDRESS
Unit
MHz min
MHz max
kHz min
MHz max
typ
ns min
ns min
min
min
ns min
ns max
min
min
ns min
ns min
max
= AV
Figure 2. Parallel Interface Timing Diagram
t
9
DD4
t
4
t
= 5 V, T
3
Figure 3. AD7762 Register Write
DATA MSW
t
Rev. 0 | Page 5 of 28
Description
Applied master clock frequency
Internal modulator clock derived from MCLK
DRDY pulse width
DRDY falling edge to CS falling edge
RD/WR setup time to CS falling edge
Data access time
CS low read pulse width
CS high pulse width between reads
RD/WR hold time to CS rising edge
Bus relinquish time
CS low write pulse width
CS high period between address and data
Data setup time
Data hold time
5
A
= 25°C, normal mode, unless otherwise noted.
t
12
t
10
t
6
REGISTER DATA
LSW + STATUS
t
7
t
8
AD7762