AD7762 Analog Devices, AD7762 Datasheet - Page 13

• Manufacturer Part Number: AD7762
• Description: Parallel Interface, 625 kSPS, 24-Bit Sigma-Delta A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7762

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (1.6Vref) p-p,4 V p-p,6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

THEORY OF OPERATION
The AD7762 employs a Σ-Δ conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word to the digital filter at a rate equal to ICLK.
Due to the high oversampling rate, that spreads the
quantization noise from 0 to f
the band of interest is reduced (
the quantization noise, a high order modulator is employed to
shape the noise spectrum; so that most of the noise energy is
shifted out of the band of interest (Figure 22 b).
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (Figure 22 c) while also
reducing the data rate from f
f
decimation rate used.
Digital filtering has certain advantages over analog filtering. It
does not introduce significant noise or distortion and can be
made perfectly linear phase.
The AD7762 employs three FIR filters in series. By using
different combinations of decimation ratios and filter selection
and bypassing, data can be obtained from the AD7762 at a large
range of data rates. The first filter receives data from the
modulator at ICLK MHz where it is decimated by four to
output data at ICLK/4 MHz. This partially filtered data can also
be output at this stage. The second filter allows the decimation
Table 6. Configuration with Default Filter
ICLK
Frequency
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
12.288 MHz
12.288 MHz
12.288 MHz
12.288 MHz
ICLK
/8 or less at the output of the filter, depending on the
Filter 1
4×
4×
4×
4×
4×
4×
4×
4×
4×
4×
4×
ICLK
ICLK
Filter 2
4×
8×
8×
16×
16×
32×
32×
8×
16×
32×
32×
Figure 22 a). To further reduce
at the input of the filter to
, the noise energy contained in
Filter 3
2×
Bypassed
2×
Bypassed
2×
Bypassed
2×
2×
2×
Bypassed
2×
Data State
Fully filtered
Partially filtered
Fully filtered
Partially filtered
Fully filtered
Partially filtered
Fully filtered
Fully filtered
Fully filtered
Partially filtered
Fully filtered
Rev. 0 | Page 13 of 28
rate to be chosen from 4× to 32×. The third filter has a fixed
decimation rate of 2×, is user programmable, and has a default
configuration. It is described in detail in the Programmable FIR
Filter section. This filter can be bypassed.
Table 6 lists some characteristics of the default filter. The group
delay of the filter is defined to be the delay to the center of the
impulse response and is equal to the computation + filter delays.
The delay until valid data is available (the DVALID status bit is
set) is equal to 2× the filter delay + the computation delay.
Computation
Delay
1.775 μs
2.6 μs
2.25 μs
4.175 μs
3.1 μs
7.325 μs
4.65 μs
3.66 μs
5.05 μs
11.92 μs
7.57 μs
BAND OF INTEREST
BAND OF INTEREST
BAND OF INTEREST
Filter Delay
44.4 μs
10.8 μs
87.6 μs
20.4 μs
174 μs
39.6 μs
346.8 μs
142.6 μs
283.2 μs
64.45 μs
564.5 μs
DIGITAL FILTER CUTOFF FREQUENCY
QUANTIZATION NOISE
NOISE SHAPING
Figure 22. Σ-Δ ADC
c.
a.
b.
Pass-Band
Bandwidth
250 kHz
140.625 kHz
125 kHz
70.3125 kHz
62.5 kHz
35.156 kHz
31.25 kHz
76.8 kHz
38.4 kHz
21.6 kHz
19.2 kHz
f
f
f
ICLK
ICLK
ICLK
Output Data
Rate (ODR)
625 kHz
625 kHz
312.5 kHz
312.5 kHz
156.25 kHz
156.25 kHz
78.125 kHz
192 kHz
96 kHz
96 kHz
48 kHz
\2
\2
\2
AD7762