AD7942 Analog Devices, AD7942 Datasheet
AD7942
Specifications of AD7942
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AD7942 Summary of contents
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... It is com- patible with 1 logic using a separate supply (VIO). The AD7942 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) package yet fits in the same size footprint as the 8-lead MSOP or SOT-23. Operation for the AD7942 is specified from − ...
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... Terminology .................................................................................... 12 Theory of Operation ...................................................................... 13 Circuit Information .................................................................... 13 Converter Operation .................................................................. 13 Typical Connection Diagram ................................................... 14 Digital Interface .......................................................................... 16 Application Hints ........................................................................... 23 Layout .......................................................................................... 23 Evaluating the Performance of AD7942 .................................. 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24 12/07—Rev Rev. A Changes to Table 1 ............................................................................. 1 Changes to General Description Section ....................................... 1 Changes to Table 6 ............................................................................. 7 Changes to Table 7 ............................................................................. 8 Changes to Circuit Information Section ..................................... 13 Changes to Table 9 ...
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... kHz REF kHz −60 dB input IN REF kHz 2 REF 250 kSPS REF VDD = 5 V Rev Page AD7942 Min Typ Max Unit 14 Bits REF −0.1 VDD + 0.1 V −0.1 +0 See the Analog Input section ...
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... AD7942 Parameter DIGITAL OUTPUTS Data Format Pipeline Delay POWER SUPPLIES VDD VIO VIO Range 4, 5 Standby Current Power Dissipation 6 TEMPERATURE RANGE Specified Performance 1 LSB means least significant bit. With input range, 1 LSB = 305.2 μV. 2 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. ...
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... CNVH t SCK t SCK t SCKL t SCKH t HSDO t DSDO DIS t SSDICNV t HSDICNV t SSCKCNV t HSCKCNV t SSDISCK t HSDISCK t DSDOSDI Rev Page AD7942 = −40°C to +85°C. A Min Typ Max Unit 0.5 2.2 μs 1.8 μs 4 μ ...
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... AD7942 1 VDD = 2 4 VIO = 2 4 VDD + 0.3 V, whichever is the lowest, unless otherwise stated, T Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO ≥ VIO ≥ 2.7 V VIO ≥ ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev Page AD7942 ...
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... VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1 analog input digital input digital output, and P = power. REF VIO 1 10 VDD SDI 2 9 AD7942 IN+ SCK 3 8 IN– SDO 4 7 GND CNV 5 6 NOTES 1. PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES ...
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... Figure 9. Histogram Input at the Code Center 0 16,384 POINT FFT VDD = V – –40 IN SNR = 84.2dB –60 THD = –101.7dB SFDR = –104.3dB –80 –100 –120 –140 –160 –180 FREQUENCY (kHz) Figure 10. FFT Plot AD7942 16,384 = 5V REF 0 0 2002 2003 = 2.5V REF = 250kSPS = 20.43kHz 100 125 ...
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... AD7942 86 SNR 85 SINAD 84 ENOB 83 82 2.0 2.5 3.0 3.5 4.0 REFERENCE VOLTAGE (V) Figure 11. SNR, SINAD, and ENOB vs. Reference Voltage 5V, –10dB REF REF 100 FREQUENCY (kHz) Figure 12. SINAD vs. Frequency REF 2.5V REF 80 75 –55 –35 – TEMPERATURE (°C) Figure 13. SNR vs. Temperature 15 ...
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... Figure 19. Offset Error and Gain Error vs. Temperature 100kSPS 105 125 0 Figure 20. t Rev Page AD7942 OFFSET ERROR GAIN ERROR –35 – 105 TEMPERATURE (°C) VDD = 2.5V, 85°C VDD = 2.5V, 25°C VDD = 5V, 85°C VDD = 5V, 25°C VDD = 3.3V, 85° ...
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... AD7942 TERMINOLOGY Linearity Error or Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ ...
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... The AD7942 is specified from 2 5.5 V and can be inter- faced to a 1.8 V, 2 digital logic housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that is space saving, yet allows flexible configurations ...
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... NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION. NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION. NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE. Transfer Functions The ideal transfer characteristic for the AD7942 is shown in Figure 23 and Table 7. 111...111 111...110 111...101 000 ...
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... AD8605, AD8615 AD8519 AD8031 Voltage Reference Input The AD7942 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source (for example, a reference buffer using the AD8031 or the AD8605 μ ...
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... VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD can be tied together. The AD7942 is indepen- dent of power supply sequencing between VIO and VDD. Additionally insensitive to power supply variations over a wide frequency range, as shown in Figure 27 ...
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... CS Mode 3-Wire Without Busy Indicator This mode is most often used when a single AD7942 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 30 and the corresponding timing diagram is shown in Figure 31. With SDI tied to VIO, a rising edge on CNV initiates a conver- sion, selects the CS mode, and forces SDO to high impedance. ...
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... AD7942 CS Mode 3-Wire with Busy Indicator This mode is most often used when a single AD7942 is connected to an SPI-compatible digital host with an interrupt input. The connection diagram is shown in Figure 32 and the corresponding timing diagram is shown in Figure 33. With SDI tied to VIO, a rising edge on CNV initiates a conver- sion, selects the CS mode, and forces SDO to high impedance ...
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... After the 14th SCK falling edge or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7942 can be read. If multiple AD7942s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile recommended to keep this contention as short as possible to limit extra power dissipation ...
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... AD7942 CS Mode 4-Wire with Busy Indicator This mode is most often used when a single AD7942 is connected to an SPI-compatible digital host with an interrupt input and to keep CNV (which is used to sample the analog input) independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired ...
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... The maximum conversion rate may be reduced due to the total readback time. For instance, with digital host setup time and 3 V interface eight AD7942s running at a conversion rate of 220 kSPS can be daisy-chained on a 3-wire port. CNV ...
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... AD7942s in the chain, provided the digital host has an acceptable hold time. For instance, with digital host setup time and interface eight AD7942s running at a conversion rate of 220 kSPS can be daisy-chained to a single 3-wire port. CNV ...
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... APPLICATION HINTS LAYOUT Design the PCB that houses the AD7942 so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7942, with all its analog signals on the left side and all its digital signals on the right side, eases this task ...
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... Temperature Range AD7942BRM –40°C to +85°C AD7942BRM-RL7 –40°C to +85°C 1 AD7942BRMZ –40°C to +85°C 1 AD7942BRMZ-RL7 –40°C to +85°C 1 AD7942BCPZRL –40°C to +85°C 1 AD7942BCPZRL7 –40°C to +85° EVAL-AD7942CBZ 1, 3 EVAL-CONTROL BRD3Z RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes ...