AD7942 Analog Devices, AD7942 Datasheet - Page 20

• Manufacturer Part Number: AD7942
• Manufacturer: Analog Devices

Specifications of AD7942

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7942
CS Mode 4-Wire with Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host with an interrupt
input and to keep CNV (which is used to sample the analog
input) independent of the signal used to select the data reading.
This requirement is particularly important in applications where
low jitter on CNV is desired. The connection diagram is shown
in Figure 36 and the corresponding timing diagram is given in
Figure 37.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
ACQUISITION
SDO
CNV
SCK
SDI
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
Figure 37. CS Mode 4-Wire with Busy Indicator, Serial Interface Timing
Figure 36. CS Mode 4-Wire with Busy Indicator Connection Diagram
t
EN
SDI
AD7942
CNV
SCK
1
Rev. B | Page 20 of 24
SDO
t
t
HSDO
DSDO
D13
2
VIO
47Ω
t
CYC
D12
but SDI must be returned low before the minimum conversion
time elapses and held low until the maximum conversion time
is completed to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low. With a pull-up on the SDO line this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7942 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK driving edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host also using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 15th SCK falling edge
or SDI going high, whichever is earlier, the SDO returns to high
impedance.
3
CS1
CONVERT
DATA IN
IRQ
CLK
ACQUISITION
DIGITAL HOST
t
ACQ
t
SCKL
t
SCKH
13
t
SCK
14
D1
15
D0
t
DIS