AD7942 Analog Devices, AD7942 Datasheet - Page 19

• Manufacturer Part Number: AD7942
• Manufacturer: Analog Devices

Specifications of AD7942

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

CS Mode 4-Wire Without Busy Indicator
This mode is most often used when multiple AD7942s are
connected to an SPI-compatible digital host. A connection
diagram using two AD7942s is shown in Figure 34 and the
corresponding timing diagram is given in Figure 35.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers.
However, SDI must be returned high before the minimum
conversion time elapses and held high until the maximum
conversion time is completed to avoid generating the busy
signal indicator. When the conversion is complete, the AD7942
SDI (CS1)
SDI (CS2)
ACQUISITION
SDO
CNV
SCK
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
t
EN
SDI
AD7942
Figure 35. CS Mode 4-Wire Without Busy Indicator, Serial Interface Timing
Figure 34. CS Mode 4-Wire Without Busy Indicator Connection Diagram
CNV
SCK
D13
1
t
HSDO
SDO
D12
2
D11
3
t
DSDO
t
SCKL
t
Rev. B | Page 19 of 24
SCKH
SDI
12
AD7942
t
SCK
CNV
SCK
13
D1
t
CYC
enters the acquisition phase and powers down. Each ADC result
can be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK driving edges. The data is valid on
both SCK edges. Although the nondriving edge can be used to
capture the data, a digital host also using the SCK falling edge
allows a faster reading rate, provided it has an acceptable hold
time. After the 14th SCK falling edge or when SDI goes high,
whichever is earlier, SDO returns to high impedance and
another AD7942 can be read.
If multiple AD7942s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
SDO
14
D0
ACQUISITION
t
ACQ
D13
15
CS2
CS1
CONVERT
DATA IN
CLK
DIGITAL HOST
D12
16
26
27
D1
28
D0
t
DIS
AD7942