AD7942 Analog Devices, AD7942 Datasheet - Page 22

• Manufacturer Part Number: AD7942
• Manufacturer: Analog Devices

Specifications of AD7942

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7942
Chain Mode with Busy Indicator
This mode can also be used to daisy-chain multiple AD7942s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applica-
tions or for systems with a limited interfacing capacity. Data
readback is analogous to clocking a shift register. A connection
diagram example using three AD7942s is shown in Figure 40
and the corresponding timing diagram is given in Figure 41.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, SDO in the near end ADC
(ADC C in Figure 40) is driven high. This transition on SDO
ACQUISITION
SDO
SDO
CNV = SDI
t
HSCKCNV
A
B
SCK
= SDI
= SDI
SDO
A
B
C
C
SDI
CONVERSION
t
t
SSCKCNV
t
CONV
DSDOSDI
AD7942
t
EN
CNV
SCK
A
t
t
t
SDO
SSDISCK
HSDO
DSDO
1
D
D
D
C
A
B
2
13 D
13 D
13 D
Figure 41. Chain Mode with Busy Indicator, Serial Interface Timing
Figure 40. Chain Mode with Busy Indicator Connection Diagram
C
A
B
3
12 D
12 D
12 D
t
SCKH
SDI
C
B
t
A
4
HSDISCK
11
11
11
AD7942
CNV
SCK
B
13
t
SCK
D
D
D
14
Rev. B | Page 22 of 24
SDO
C
B
A
1
1
1
t
SCKL
D
D
D
15
C
B
A
0
0 D
0
D
ACQUISITION
16
B
A
13 D
13 D
t
CYC
can be used as a busy indicator to trigger the data readback
controlled by the digital host. The AD7942 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are then clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first, and
14 × N + 1 clocks are required to readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host also using the SCK falling edge allows a faster
reading rate and consequently more AD7942s in the chain,
provided the digital host has an acceptable hold time. For
instance, with a 5 ns digital host setup time and a 3 V interface,
up to eight AD7942s running at a conversion rate of 220 kSPS
can be daisy-chained to a single 3-wire port.
17
B
A
SDI
t
12
12
ACQ
AD7942
27
CNV
SCK
C
D
D
28
B
A
1
SDO
1
D
D
29
B
A
0 D
0
31
A
13
D
35
A
12
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST
41
t
D
DSDOSDI
42
t
A
DSDOSDI
1
t
DSDOSDI
D
43
A
0