AD9861 Analog Devices, AD9861 Datasheet - Page 25

• Manufacturer Part Number: AD9861
• Manufacturer: Analog Devices

Specifications of AD9861

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

DAC Equivalent Circuits
The AD9861 Tx path consisting of dual 10-bit DACs is shown
in Figure 73. The DACs integrate a high performance TxDAC
core, a programmable gain control through a programmable
gain amplifier (TxPGA), coarse gain control, and offset adjust-
ment and fine gain control to compensate for system mismatches.
Coarse gain applies a gross scaling to either DAC by 1×, (1/2)×,
or (1/11)×. The TxPGA provides gain control from 0 dB to
–20 dB in steps of 0.1 dB and is controlled via the 8-bit TxPGA
setting. A fine gain adjustment of ±4% for each channel is con-
trolled through a 6-bit fine gain register. By default, coarse gain
is 1×, the TxPGA is set to 0 dB, and the fine gain is set to 0%.
The TxDAC core of the AD9861 provides dual, differential,
complementary current outputs generated from the 10-bit data.
The 10-bit dual DACs support update rates up to 200 MSPS.
The differential outputs (IOUT+ and IOUT–) of each dual DAC
are complementary, meaning that they always add up to the full-
scale current output of the DAC, I
loads or a transformer.
The fine gain control provides improved balance of QAM
modulated signals, resulting in improved modulation accuracy
and image rejection.
The independent DAC A and DAC B offset control adds a small
dc current to either IOUT+ or IOUT– (not both). The selection
of which IOUT this offset current is directed toward is
programmable via register setting. Offset control can be used
for suppression of an LO leakage signal that typically results at
the output of the modulator. If the AD9861 is dc-coupled to an
external modulator, this feature can be used to cancel the output
offset on the AD9861 as well as the input offset on the modulator.
The reference circuitry is shown in Figure 74.
REFERENCE
Figure 73. TxDAC Output Structure Block Diagram
TxDAC
TxDAC
BIAS
OFFSET
OFFSET
DAC
DAC
PGA
PGA
OUTFS
+
+
. Optimum ac performance
+
+
+
+
+
+
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IOUT+A
IOUT–A
IOUT+B
IOUT–B
Rev. 0 | Page 25 of 52
Referring to the transfer function of the following equation,
I
default gain setting (0 dB), and is based on a reference current,
I
R
Typically, R
optimal dynamic setting for the TxDACs. Increasing R
factor of 2 proportionally decreases I
I
using the TxPGA gain register or independently using the
DAC A/DAC B coarse gain registers.
The TxPGA function provides 20 dB of simultaneous gain
range for both DACs, and is controlled by writing to the SPI
register TxPGA gain for a programmable full-scale output of
10% to 100% of I
steps of about 0.1 dB. Internally, the gain is controlled by
changing the main DAC bias currents with an internal TxPGA
DAC whose output is heavily filtered via an on-chip R-C filter
to provide continuous gain transitions. Note that the settling
time and bandwidth of the TxPGA DAC can be improved by a
factor of 2 by writing to the TxPGA fast register.
Each DAC has independent coarse gain control. Coarse gain
control can be used to accommodate different I
dual DACs. The coarse full-scale output control can be adjusted
by using the DAC A/DAC B coarse gain registers to 1/2 or 1/11
of the nominal full-scale current.
Fine gain controls and dc offset controls can be used to
compensate for mismatches (for system level calibration),
allowing improved matching characteristics of the two Tx
channels and aiding in suppressing LO feedthrough. This is
especially useful in image rejection architectures. The 10-bit dc
offset control of each DAC can be used independently to
provide an offset of up to ±12% of I
pin, thus allowing calibration of any system offsets. The fine
gain control with 5-bit resolution allows the I
DAC to be varied over a ±4% range, allowing compensation of
any DAC or system gain mismatches. Fine gain control is set
through the DAC A/DAC B fine gain registers, and the offset
control of each DAC is accomplished using the DAC A/DAC B
offset registers.
OUTFSMAX
REF
OUTFSMAX
SET
0.1µF
. I
I
resistor.
OUTFSMAX
REF
is set by the internal 1.2 V reference and the external
is the maximum current output of the DAC with the
of each DAC can be rescaled either simultaneously
SET
= 64 × ( REFIO/R
REFIO
FSADJ
R
SET
is 4 kΩ, which sets I
OUTFSMAX
≥
4kΩ
Figure 74. Reference Circuitry
. The gain curve is linear in dB, with
REFERENCE
1.2V
SET
)
OUTFSMAX
OUTFSMAX
OUTFSMAX
REFERENCE BIASES
DAC A AND DAC B
SOURCE ARRAY
to 20 mA, the
CURRENT
I
to either differential
REF
by a factor of 2.
OUTFSMAX
OUTFS
AD9861
from the
of each
I
OUTFSMAX
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SET
by a