AD9861 Analog Devices, AD9861 Datasheet - Page 45

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AD9861

Manufacturer Part Number
AD9861
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD9861

Resolution (bits)
10bit
# Chan
2
Sample Rate
80MSPS
Interface
Par
Analog Input Type
Diff-Uni
Ain Range
2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP

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CLOCK DISTRIBUTION BLOCK
Theory/Description
The AD9861 uses a clock distribution block to distribute the
timing derived from the input clock (applied to the CLKIN pin,
referred to here as CLKIN) to the Rx and Tx paths. There are
many options for configuring the clock distribution block,
which are available through internal register settings. The Clock
Distribution Block Diagram section describes the timing block
diagram breakdown, followed by the data timing for the
different data interface options.
The clock distribution block contains a PLL, which includes an
optional output divide-by-5 circuit, an ADC divide-by-2 circuit,
multiplexers, and other digital logic.
There are two main methods of configuring the Rx path timing
of the AD9861, normal timing mode and alternative timing
mode, which are controlled through register Alt timing mode
[Register 0x15, Bit 4]. In normal timing mode, the Rx path clock
is driven directly from the CLKIN input and the Tx path is
driven by a clock derived from CLKIN multiplied by the on
chip PLL. In alternative timing mode, the input clock is applied
to the PLL circuitry, and the PLL output clock drives both the
Rx path clock and Tx path clock.
Because alternative timing mode uses the PLL to derive the Rx
path clock, the ADC performance may degrade slightly. This
degradation is due to the phase noise from the PLL. Typically it
occurs in undersampling applications when the input signal is
above the first Nyquist zone of the ADC.
The PLL can provide 1×, 2×, 4×, 8×, and 16× multiplication or
can be bypassed and powered down through register PLL
bypass [Register 0x15, Bit 7] and through register PLL power-
down [Register 0x2, Bit 2]. The PLL requires a minimum input
clock frequency of 16 MHz and needs to provide a minimum
PLL output clock of 32 MHz. This limit applies to the PLL
output prior to the optional divide-by-5 circuitry. For clock
frequencies below these limits, the PLL must be bypassed. The
PLL maximum output frequency before the divide-by-5 cir-
cuitry is 350 MHz. Table 21 shows the input and output clock
rates for all the multiplication settings.
Rev. 0 | Page 45 of 52
Table 21. PLL Input and Output Minimum and Maximum
Clock Rates
PLL Setting
1× (PLL Bypassed)
1× (PLL Enabled)
* 1/5 ×
* 2/5 ×
* 4/5 ×
* 8/5 ×
* 16/5 ×
* Indicates PLL output divide-by-5 circuit enabled.
Clock Distribution Block Diagram
The Clock Distribution Block diagram is shown in
Figure 84. An output clock formatter configures the output
synchronization signals, IFACE1, IFACE2, and IFACE3. These
interface pin signals depend on clock mode setting, data I/O
configuration, and other operational settings. Clock mode and
data I/O configuration are defined in register settings of
clk_mode, SpiFDnHD, and SpiB10n20.
Table 22 shows the configuration of the IFACE1, IFACE2 and
IFACE3 pins relative to clock mode (for half-duplex cases, the
IFACE1 pin is an input that identifies if the device is in Rx or Tx
operation mode). The clock mode is used to specify the timing
for each data interface operation modes, which are discussed in
detail in the Flexible I/O Interface Options section. The T and R
extensions after the half-duplex Modes 4, 5, 7, 8, and 10 in the
Table 22 indicate that the device is in transmit or receive
operation mode. The default clock mode setting [Register 0x01,
Bits 5–7, clk_mode] of ‘000’ configures clock Mode 1 for the
full-duplex operation, Mode 4 for half-duplex 20 operation and
Mode 7 for half-duplex 10 operation. Modes 2, 5, 8, and 10 are
optional timing configurations for the AD9861 that can be
programmed through Register 0x01 clk_mode.
Input Clock
(Min/Max) (MHz)
1/200
32/200
16/100
16/50
16/25
32/200
16/175
16/87.5
16/43.75
16/21.875
Output Clock
(Min/Max) (MHz)
1/200
32/200
32/200
64/200
128/200
6.4/40
6.4/70
12.8/70
25.6/70
51.2/70
AD9861

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