AD9861 Analog Devices, AD9861 Datasheet - Page 46

• Manufacturer Part Number: AD9861
• Manufacturer: Analog Devices

Specifications of AD9861

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9861
Table 22. Interface Pins (IFACE1, IFACE2, IFACE3) Configuration Definition for Flexible Interface Operation
Clock
Mode
PIN
IFACE1
IFACE2
IFACE3
The Tx clock output frequency depends on whether the data is
in interleaved or parallel (noninterleaved) configuration. Modes
1, 2, 7, 8, and 10 use Tx interleaved data and require either 2× or
4× interpolation to be enabled.
•
•
•
The Rx clock does not depend on whether the data is inter-
leaved or parallel, but does depend on the configuration of the
timing mode: normal or alternative.
•
•
DAC update rate = CLKIN × PLL setting.
Noninterleaved Tx data clock frequency = CLKIN × PLL
setting × 1/(interpolation rate).
Interleaved Tx data clock frequency = 2 × CLKIN × PLL
setting × 1/(interpolation rate).
Normal timing mode, Rx clock frequency = CLKIN × ADC
Div factor (if enabled).
Alternative timing mode, Rx clock frequency = CLKIN ×
PLL setting × ADC Div factor (if enabled).
1
Full-Duplex
TxSync
Buff_CLKIN
Tx Clock
CLKIN
2
RxSync
1. ALTERNATE TIMING MODE: REG 0x15, BIT 4
2. PLL MULTIPLICATION SETTING: REG 0x15, BITS 2–0
3. PLL OUTPUT DIVIDE BY 5; REG 0x15, BIT 3
4. Rx PATH DIVIDE BY 2: REG 0x15, BIT 5
5. PLL BYPASS PATH: REG 0x15, BIT 7
6. INTERP CONTROL, Tx/Rx INV IFACE3, CLK MODE, INV IFACE2, FD/HD, 10/20
4T
Half-Duplex, 20-Bit
Tx/ Rx
Optional CLKOUT
Tx
Clock
1, 2, 4, 8, 16
1
2
4R
Rx
Clock
Figure 84. Clock Distribution Block Diagram
1, 5
3
5T
Tx
Clock
1, 2
4
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5
80MHz MAX
5R
Rx
Clock
An optional CLKOUT from IFACE2 is available as a stable
system clock running at the CLKIN frequency or the TxDAC
update rate, which is equal to CLKIN × PLL setting. Setting the
enable IFACE2 register [Register 0x01, Bit 2] enables the
IFACE2 optional clock output. In FD mode, the IFACE2 pin
always acts as a clock output; the enable IFACE2 pin can be
used to invert the IFACE2 output.
Configuration
The AD9861 timing for the transmit path and for the receive
path depend on the mode setting and various programmable
options. The registers that affect the output clock timing and
data input/output timing are clk_mode [2:0]; enable IFACE2;
inv clkout (IFACE3); Tx inverse sample; interpolation control;
PLL bypass; ADC clock div; Alt timing mode; PLL Div5; PLL
multiplication; and PLL to IFACE2. The clk_mode register is
discussed previously. Table 23 shows the other register bits that
are used to configure the output clock timing and data latching
options available in the AD9861.
DIGITAL
DIGITAL
BLOCK
BLOCK
Rx
Tx
7T
Half-Duplex, 10-Bit
Tx/ Rx
Optional CLKOUT
Tx
Clock
Rx
PATH
Tx
PATH
7R
Rx
Clock
FORMATTER
OUTPUT
CLOCK
6
8T
Tx
Clock
IFACE2
IFACE3
8R
Rx
Clock
10T
Clone Mode
Tx/ Rx
Optional CLKOUT
Tx
Clock
10R
Rx
Clock